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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id h6sm1125174otb.60.2021.12.16.10.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 10:44:59 -0800 (PST) From: Chris Morgan To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, miquel.raynal@bootlin.com, wd@denx.de, sjg@chromium.org, Chris Morgan Subject: [PATCH v4 3/3] mtd: Add pairing info for Hynix H27UCG8T2ETR NAND Date: Thu, 16 Dec 2021 12:44:48 -0600 Message-Id: <20211216184448.27193-4-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211216184448.27193-1-macroalpha82@gmail.com> References: <20211216184448.27193-1-macroalpha82@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Chris Morgan Add pairing info for the Hynix H27UCG8T2ETR NAND so that we may utilize slc-mode emulation for enhanced reliability and compatibility with upstream Linux. I have checked with the team at #mtd and they can confirm based on a cursory reading of the datasheet for this flash chip it appears to use the same dist3 pairing scheme used by the Toshiba NAND which already supports dist3 today in mainline Linux. Signed-off-by: Chris Morgan --- drivers/mtd/nand/raw/nand_base.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 7fdb08e4df..20f54444ef 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4551,6 +4551,14 @@ ident_done: mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme); } + /* Enable slc-mode on H27UCG8T2ETR to enable upstream Linux */ + if (id_data[0] == NAND_MFR_HYNIX && id_data[1] == 0xde + && id_data[2] == 0x14 && id_data[3] == 0xa7 + && id_data[4] == 0x42 && id_data[5] == 0x4a) { + chip->options |= NAND_NEED_SCRAMBLING; + mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme); + } + if (chip->options & NAND_BUSWIDTH_AUTO) { WARN_ON(chip->options & NAND_BUSWIDTH_16); chip->options |= busw; -- 2.30.2