From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E8DEC433F5 for ; Tue, 21 Dec 2021 11:20:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 887678304F; Tue, 21 Dec 2021 12:20:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="W/tu67ZQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3E2A583492; Tue, 21 Dec 2021 12:20:49 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A83B38303D for ; Tue, 21 Dec 2021 12:20:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8C21E6140D; Tue, 21 Dec 2021 11:20:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D11B8C36AE8; Tue, 21 Dec 2021 11:20:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640085643; bh=3nuZKkptJFC11jom5/8HVEsC3eqr4Z/9vXPLnrp9SKQ=; h=From:To:Cc:Subject:Date:From; b=W/tu67ZQNvLuD3j4v/JNOaQhddZyl7jlvLDGsZAl11pZW6aSWyOrvu7GsF9dpDrde WhYfY2u1nSnCu/QI87s+dLZSr7Y9rUQRqsF1LepqE0SpjE+J4eZomqWo+d5+4PYPuG WazBla/+vJApjVDsN450e+m/trVI8BSKULYXsriCrNW2H+CeoSzuC/ifM+TqnxFt9V OO8l+IIEDAVXzHLHNBQqxdxMiXY9fwgq9YN+BwuPpT1wkiHw5hTzCx0F67dIlTSMS+ o0Mkb6XhIrEnG7falGhJO9Ba1VjgpIDNLomqA95uVUB38vmXq1nJfcbVUwGb1Okhv7 yAH3hi2W3RlNw== Received: by pali.im (Postfix) id 42453778; Tue, 21 Dec 2021 12:20:40 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , Dirk Eibach , Mario Six , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Chris Packham Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 0/9] mvebu: Move PCIe code from serdes to PCIe driver Date: Tue, 21 Dec 2021 12:20:10 +0100 Message-Id: <20211221112019.15088-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This patch series removes gdsys's board_pex_config() function by converting it to spl_board_init(), adds a new mvebu-reset driver for enabling / disabling PCIe ports and finally moves PCIe code from serdes driver to pci_mvebu.c driver. After all these changes, PCIe link is not initialized in serdes code anymore, but in pci_mvebu.c driver with help of mvebu-reset driver. I'm not sure if change for gdsys board is correct, so if somebody has this board, please test it. I tested this change on A385 board Turris Omnia and I verified that PCIe links are really enabled by pci_mvebu.c driver and not before. This patch series is based on u-boot-marvell/next branch. Pali Rohár (9): arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT board: gdsys: a38x: Enable PCIe link 2 in spl_board_init() pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro pci: pci_mvebu: Split initialization of PCIe ports into 3 phases pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c arch/arm/dts/armada-375.dtsi | 5 +- arch/arm/dts/armada-380.dtsi | 3 + arch/arm/dts/armada-385.dtsi | 4 + arch/arm/dts/armada-38x.dtsi | 1 + arch/arm/dts/armada-xp-98dx3236.dtsi | 2 + arch/arm/dts/armada-xp-mv78230.dtsi | 5 + arch/arm/dts/armada-xp-mv78260.dtsi | 9 + arch/arm/dts/armada-xp-mv78460.dtsi | 10 + arch/arm/dts/armada-xp-synology-ds414.dts | 1 + arch/arm/dts/armada-xp-theadorable.dts | 1 + arch/arm/dts/armada-xp.dtsi | 1 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/include/mach/cpu.h | 5 +- arch/arm/mach-mvebu/serdes/a38x/Makefile | 1 - arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 64 ---- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 28 -- .../serdes/a38x/high_speed_env_spec.c | 19 -- arch/arm/mach-mvebu/system-controller.c | 105 +++++++ board/gdsys/a38x/controlcenterdc.c | 6 +- configs/controlcenterdc_defconfig | 1 + drivers/pci/Kconfig | 1 + drivers/pci/pci_mvebu.c | 275 ++++++++++++++---- 22 files changed, 371 insertions(+), 177 deletions(-) delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h create mode 100644 arch/arm/mach-mvebu/system-controller.c -- 2.20.1