From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97901C433FE for ; Tue, 21 Dec 2021 11:21:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7094F8309A; Tue, 21 Dec 2021 12:20:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="WwEgG1eo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3647C8304F; Tue, 21 Dec 2021 12:20:50 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4DD7482FC8 for ; Tue, 21 Dec 2021 12:20:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CF9EAB81648; Tue, 21 Dec 2021 11:20:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8210CC36AEC; Tue, 21 Dec 2021 11:20:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640085643; bh=DEmMSEQQaolJyCmHbY+Sq36DAztvWmKd06jeX/1ekgg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WwEgG1eo/6g+PDqmkdHLgACOk6Peyzftmm9eip9ZFxepWajoqHrogPiu1Y7iOSwXl 614S9RL85HWz5+SJasOvrEWYsvnmLsah6nc2aGgAOsprqk7nX65794DVdro6uFtSEy H2nrBQSeE8ZB2RG4S2zQ5d3YMTovaOoUSojETrTuzpgtdMraGa63JpUgRqpcx1EIkY 8kIyjyagLl5Dn5mZ6o5Z5ag4Y8BQOpnyhXrcAzMD1YBf09I31m2BtBdAbkkZIwPyGz Qg/Xxcr5vUfpxtPkzJHn3roFIkt01JpJOnhoEsHRSZ0foNkohHWy0n7jpmdEkffslP Jaf79+Fw3q32Q== Received: by pali.im (Postfix) id 3427C284E; Tue, 21 Dec 2021 12:20:41 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , Dirk Eibach , Mario Six , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Chris Packham Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 2/9] board: gdsys: a38x: Enable PCIe link 2 in spl_board_init() Date: Tue, 21 Dec 2021 12:20:12 +0100 Message-Id: <20211221112019.15088-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221112019.15088-1-pali@kernel.org> References: <20211221112019.15088-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean A385 controlcenterdc board does not use PCI DM properly and touches some PCIe devices directly in its board code. This controlcenterdc spl_board_init() function expects that PCIe link is already initialized. Link itself is initialized in a38x serdes code but this will change in future and link initialization will be postponed from U-Boot SPL to proper U-Boot. So explicitly enable PCIe link 2 in spl_board_init() function via SoC Control Register 1 to not break this code by future changes. This board has PCIe link 2 just x1, so no additional initialization (except enabling PCIe port) is needed. Signed-off-by: Pali Rohár --- board/gdsys/a38x/controlcenterdc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 243d02232667..7d65400ccb0d 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -100,6 +100,10 @@ void spl_board_init(void) uint k; struct gpio_desc gpio = {}; + /* Enable PCIe link 2 */ + setbits_32(MVEBU_REGISTER(0x18204), BIT(2)); + mdelay(10); + if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) { /* prepare FPGA reconfiguration */ dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); -- 2.20.1