From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0271DC433EF for ; Mon, 3 Jan 2022 00:10:19 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AEF4081420; Mon, 3 Jan 2022 01:10:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OobVkWEz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D61038141B; Mon, 3 Jan 2022 01:10:15 +0100 (CET) Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B1FFA82F5E for ; Mon, 3 Jan 2022 01:10:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jbx6244@gmail.com Received: by mail-ed1-x52c.google.com with SMTP id w16so129947767edc.11 for ; Sun, 02 Jan 2022 16:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QD3EgfPFXpcxinfwBiBsXU46aDhO37TWUJQb6ltVEJ8=; b=OobVkWEz3wQgfmXrZPNpHrLS3MGSA9JSpgR54U+Anhbf79Crt+ffqYXODRAEZja7zu bLKsI8vZYtr7E41o8emRGB7m/j7reuNoDncy0QyiyShWbJjYfHiU1jIriDflnY6D7GBd ajo0t2EtD4tPnh/iH7Out1XRQcBGQTGPg5hNfRdlpN5BhRmjJceOtNwXtX8rtg78/UkR Co9y8IIlxMa+RNep8N3t+9I6h4Ar2tW+a5bGFoFPoD2nXXXUVmYsbUkVQRXUF2W/E6R2 rI4hN7WL8pU9CPi+vLyaz5J0XKKA8RFtBvox+IMkrJV22RMXa7e0UiyuX/rccNljjF2r boIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QD3EgfPFXpcxinfwBiBsXU46aDhO37TWUJQb6ltVEJ8=; b=IHaFwuFNsp58ylWl6WFyQryGS4cJCpwiGWkkxdhvNMmra/lCB7gnO1lG2r/mQEJPgy 0psNkOJW/Yp87qlto/fZtaK+iwAXudMJObTcL0C/1tKp+5Uqmkf+RpQ/Q1gQ3AnUYnIX nJ/rfjA2kuC0zalcYgQlO6GzA4EwIiTLKvEDT1yiUX3j2Kf3J9MJRAwplQ6ZDKODyZ+D QLDVTr/L40SBFbtl8WYxnTKwX8/z7QXhGn79SKs/VrYzoqUW6fYFLDBaMOT0z+9vxcIi 1cs5JYzkHnVk06Nhm++s7naK0ziQYt8VmfOjhTe5bC5Pm+8niix4YZ3Oh5teBNC0AewP 8B2w== X-Gm-Message-State: AOAM5307QsmIo4/4IeuJiO6WCHl4uod7MuKFZiHGOT9vua+bDU1ZJqWj 4njIbO9rb8B08Z1JOoIyJjkzaAJguo450g== X-Google-Smtp-Source: ABdhPJwDXW1Nei52g8+Wb9kTX6MIeqpCH1elKNB0MibVwAwomMKlnEt524Uej3smxcSiRjvxWSmlRQ== X-Received: by 2002:a17:907:7dac:: with SMTP id oz44mr33494340ejc.307.1641168612322; Sun, 02 Jan 2022 16:10:12 -0800 (PST) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id b4sm10180183ejl.129.2022.01.02.16.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jan 2022 16:10:12 -0800 (PST) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, marex@denx.de, u-boot@lists.denx.de Subject: [PATCH v1] rockchip: timer: add OF_PLATDATA support for dw-apb-timer Date: Mon, 3 Jan 2022 01:10:05 +0100 Message-Id: <20220103001005.1527-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The Rockchip rk3066 SoC has 3 dw-apb-timer nodes. U-boot is compiled with OF_PLATDATA TPL/SPL options, so add OF_PLATDATA support for the dw-apb-timer. Also change driver name to be able to compile with U-boot scripts. No reset OF_PLATDATA support was added, because the rk3066 nodes don't need/have them. Signed-off-by: Johan Jonker --- drivers/timer/dw-apb-timer.c | 52 ++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 9aed5dd2..80fa5760 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -25,6 +27,12 @@ struct dw_apb_timer_priv { struct reset_ctl_bulk resets; }; +struct dw_apb_timer_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_snps_dw_apb_timer dtplat; +#endif +}; + static u64 dw_apb_timer_get_count(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); @@ -43,20 +51,33 @@ static int dw_apb_timer_probe(struct udevice *dev) struct dw_apb_timer_priv *priv = dev_get_priv(dev); struct clk clk; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dw_apb_timer_plat *plat = dev_get_plat(dev); + struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat; - ret = reset_get_bulk(dev, &priv->resets); - if (ret) - dev_warn(dev, "Can't get reset: %d\n", ret); - else - reset_deassert_bulk(&priv->resets); + priv->regs = dtplat->reg[0]; - ret = clk_get_by_index(dev, 0, &clk); - if (ret) + ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk); + if (ret < 0) return ret; - uc_priv->clock_rate = clk_get_rate(&clk); + uc_priv->clock_rate = dtplat->clock_frequency; +#endif + if (IS_ENABLED(OF_REAL)) { + ret = reset_get_bulk(dev, &priv->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; - clk_free(&clk); + uc_priv->clock_rate = clk_get_rate(&clk); + + clk_free(&clk); + } /* init timer */ writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); @@ -68,9 +89,11 @@ static int dw_apb_timer_probe(struct udevice *dev) static int dw_apb_timer_of_to_plat(struct udevice *dev) { - struct dw_apb_timer_priv *priv = dev_get_priv(dev); + if (IS_ENABLED(OF_REAL)) { + struct dw_apb_timer_priv *priv = dev_get_priv(dev); - priv->regs = dev_read_addr(dev); + priv->regs = dev_read_addr(dev); + } return 0; } @@ -91,13 +114,14 @@ static const struct udevice_id dw_apb_timer_ids[] = { {} }; -U_BOOT_DRIVER(dw_apb_timer) = { - .name = "dw_apb_timer", +U_BOOT_DRIVER(snps_dw_apb_timer) = { + .name = "snps_dw_apb_timer", .id = UCLASS_TIMER, .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, .of_match = dw_apb_timer_ids, - .of_to_plat = dw_apb_timer_of_to_plat, + .of_to_plat = dw_apb_timer_of_to_plat, .remove = dw_apb_timer_remove, .priv_auto = sizeof(struct dw_apb_timer_priv), + .plat_auto = sizeof(struct dw_apb_timer_plat), }; -- 2.20.1