From: "Marek Behún" <kabel@kernel.org>
To: "Chris Packham" <judge.packham@gmail.com>,
"Chris Packham" <chris.packham@alliedtelesis.co.nz>,
"Stefan Roese" <sr@denx.de>, "Baruch Siach" <baruch@tkos.co.il>,
"Pavol Rohár" <pali@kernel.org>,
u-boot@lists.denx.de, "Mario Six" <mario.six@gdsys.cc>,
"Dennis Gilmore" <dgilmore@redhat.com>,
"Kostya Porotchkin" <kostap@marvell.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Subject: [PATCH u-boot-marvell] PLEASE TEST ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
Date: Tue, 4 Jan 2022 21:28:27 +0100 [thread overview]
Message-ID: <20220104202827.9120-1-kabel@kernel.org> (raw)
From: Marek Behún <marek.behun@nic.cz>
Hello,
continuing my last discussion with Chris [1] about this, could you
please test this change? (For Chris, mainly on your x530, since last
time you said it hanged your board in SPL.)
It should fix DDR3 training issues.
[1] https://lore.kernel.org/u-boot/20210208191225.14645-1-marek.behun@nic.cz/
Signed-off-by: Marek Behún <marek.behun@nic.cz>
---
.../a38x/ddr3_training_centralization.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
index 648b37ef6f..ed799757b9 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
@@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
u32 if_id, pattern_id, bit_id;
u8 bus_id;
+ u8 current_byte_status;
u8 cur_start_win[BUS_WIDTH_IN_BITS];
u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
u8 cur_end_win[BUS_WIDTH_IN_BITS];
@@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
result[search_dir_id][7]));
}
+ current_byte_status =
+ mv_ddr_tip_sub_phy_byte_status_get(if_id,
+ bus_id);
+
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
bit_id++) {
/* check if this code is valid for 2 edge, probably not :( */
@@ -174,11 +179,33 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
[HWS_LOW2HIGH]
[bit_id],
EDGE_1);
+ if (current_byte_status &
+ (BYTE_SPLIT_OUT_MIX |
+ BYTE_HOMOGENEOUS_SPLIT_OUT)) {
+ if (cur_start_win[bit_id] >= 64)
+ cur_start_win[bit_id] -= 64;
+ else
+ cur_start_win[bit_id] = 0;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n",
+ pattern_id, if_id, bus_id, bit_id));
+ }
cur_end_win[bit_id] =
GET_TAP_RESULT(result
[HWS_HIGH2LOW]
[bit_id],
EDGE_1);
+ if (cur_end_win[bit_id] >= 64 &&
+ (current_byte_status &
+ BYTE_SPLIT_OUT_MIX)) {
+ cur_end_win[bit_id] -= 64;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n",
+ pattern_id, if_id, bus_id, bit_id));
+ }
+
/* window length */
current_window[bit_id] =
cur_end_win[bit_id] -
--
2.34.1
next reply other threads:[~2022-01-04 20:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 20:28 Marek Behún [this message]
2022-01-04 22:10 ` [PATCH u-boot-marvell] PLEASE TEST ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision Chris Packham
2022-01-05 9:10 ` Marek Behún
2022-01-05 22:51 ` Chris Packham
2022-01-06 3:04 ` Chris Packham
-- strict thread matches above, loose matches on Subject: below --
2021-02-08 19:12 Marek Behún
2021-02-08 19:15 ` Marek Behun
2021-02-08 20:14 ` Chris Packham
2021-02-08 20:24 ` Marek Behun
2021-06-28 7:20 ` Pali Rohár
2021-06-28 9:21 ` Chris Packham
2021-06-28 9:53 ` Chris Packham
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