From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B96FCC433FE for ; Tue, 4 Jan 2022 20:28:42 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CEAC383025; Tue, 4 Jan 2022 21:28:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="XVSvASYG"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C3F6E81C08; Tue, 4 Jan 2022 21:28:37 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7759581C08 for ; Tue, 4 Jan 2022 21:28:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kabel@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 16DAFB81240; Tue, 4 Jan 2022 20:28:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CADC8C36AE0; Tue, 4 Jan 2022 20:28:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641328112; bh=5o9kQ3DNS0cFmZC09CdbpR+0sxzw06aUsqdDWWF2ju4=; h=From:To:Cc:Subject:Date:From; b=XVSvASYGJuXWnwgE5yYDPhvipwO1Zsx0jqwQoKyQkx8pa/mtrzdgIlnITSX8N32fI 83fb537wi8zJDUfGbRkRtVT7PyB/J+5szRauIZJUNLqyQ9V8o82NCpq9KMZTBjewVx ufi8Dw2Tk3MUfhaAscpj4etc/4Sfn0sUJt5QBhzHdVpPMwpUUIgPsCif0R9r33aF7t i37x9FGngFv5YXC7lIoTrRxL4ccsCgkuLkH7/ihT3nPdNIO/wUbvEDNx4dbI/LDO5K KofHoneeQjYU+rfkFlI7+Q1fMQGqSvu2Y7cKff0BfbdUDF/5Tx7BjuikXwHroYFbat hUhqk1LCYGydw== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Chris Packham , Chris Packham , Stefan Roese , Baruch Siach , =?UTF-8?q?Pavol=20Roh=C3=A1r?= , u-boot@lists.denx.de, Mario Six , Dennis Gilmore , Kostya Porotchkin Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH u-boot-marvell] PLEASE TEST ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision Date: Tue, 4 Jan 2022 21:28:27 +0100 Message-Id: <20220104202827.9120-1-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Behún Hello, continuing my last discussion with Chris [1] about this, could you please test this change? (For Chris, mainly on your x530, since last time you said it hanged your board in SPL.) It should fix DDR3 training issues. [1] https://lore.kernel.org/u-boot/20210208191225.14645-1-marek.behun@nic.cz/ Signed-off-by: Marek Behún --- .../a38x/ddr3_training_centralization.c | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c index 648b37ef6f..ed799757b9 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c @@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; u32 if_id, pattern_id, bit_id; u8 bus_id; + u8 current_byte_status; u8 cur_start_win[BUS_WIDTH_IN_BITS]; u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; u8 cur_end_win[BUS_WIDTH_IN_BITS]; @@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) result[search_dir_id][7])); } + current_byte_status = + mv_ddr_tip_sub_phy_byte_status_get(if_id, + bus_id); + for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) { /* check if this code is valid for 2 edge, probably not :( */ @@ -174,11 +179,33 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) [HWS_LOW2HIGH] [bit_id], EDGE_1); + if (current_byte_status & + (BYTE_SPLIT_OUT_MIX | + BYTE_HOMOGENEOUS_SPLIT_OUT)) { + if (cur_start_win[bit_id] >= 64) + cur_start_win[bit_id] -= 64; + else + cur_start_win[bit_id] = 0; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_INFO, + ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n", + pattern_id, if_id, bus_id, bit_id)); + } cur_end_win[bit_id] = GET_TAP_RESULT(result [HWS_HIGH2LOW] [bit_id], EDGE_1); + if (cur_end_win[bit_id] >= 64 && + (current_byte_status & + BYTE_SPLIT_OUT_MIX)) { + cur_end_win[bit_id] -= 64; + DEBUG_CENTRALIZATION_ENGINE + (DEBUG_LEVEL_INFO, + ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n", + pattern_id, if_id, bus_id, bit_id)); + } + /* window length */ current_window[bit_id] = cur_end_win[bit_id] - -- 2.34.1