From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74316C433EF for ; Wed, 5 Jan 2022 09:50:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0623982F91; Wed, 5 Jan 2022 10:50:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="JmdlwUD5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7FCA183146; Wed, 5 Jan 2022 10:50:39 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF48E82F91 for ; Wed, 5 Jan 2022 10:50:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 77A98B810B6; Wed, 5 Jan 2022 09:50:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 165FCC36AEB; Wed, 5 Jan 2022 09:50:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641376235; bh=I6edGP54nljS/FpHj6h1Alt2/556qfBKjfO+MPepdWw=; h=From:To:Cc:Subject:Date:From; b=JmdlwUD5PpaOjvQKMkN/LtlcEcdaLercpQgMoefAaH1C0rYNKDde2eJKE8NDg/asi 4QcBZatOvo2qhOVgx2hS/hgte6HjhXbVLUn0CZu/4jeLS5sVnwO1EnUTiTIob3ugQs q+X15MaBocStqyZ/alAKlXysWn0hcOoJNqFmJClT83LIQ/FR3cxWVpv8w+Lo+1TCF4 vVTSjzov6vy7ic+5lfc16IOkFCkayJv3gqz2onVYIhljgWL0jdmvqutf9NF1mtqjmD NYTkCONntduvfjI60j2wdykDSk3Du6+fBZjHGIX2m1G2XwBPOxyTU42mG07p57hM3S zLMiKitg8oz1Q== Received: by pali.im (Postfix) id E22ED82A; Wed, 5 Jan 2022 10:50:32 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Roman Bacik , Bharat Gooty , Simon Glass , Stefan Roese Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-pci] pci: iproc: Set all 24 bits of PCI class code Date: Wed, 5 Jan 2022 10:50:20 +0100 Message-Id: <20220105095020.28249-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Register 0x43c in its low 24 bits contains PCI class code. Update code to set all 24 bits of PCI class code and not only upper 16 bits of PCI class code. Use standard U-Boot macro (PCI_CLASS_BRIDGE_PCI << 8) for constructing all 24-bits of PCI class for PCI bridge Normal decode. Signed-off-by: Pali Rohár --- Roman helped me with this change and confirmed that class code is stored really in bits [23:0] of custom register 0x43c (normally class code is stored in bits [31:8] of pci register 0x08). --- drivers/pci/pcie_iproc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index be03dcbd97c0..fe68e417ae80 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -1127,15 +1127,14 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) u32 link_status, class; pcie->link_is_active = false; - /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ + /* force class to PCI bridge Normal decode (0x060400) */ #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c -#define PCI_CLASS_BRIDGE_MASK 0xffff00 -#define PCI_CLASS_BRIDGE_SHIFT 8 +#define PCI_BRIDGE_CTRL_REG_CLASS_MASK 0xffffff iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, &class); - class &= ~PCI_CLASS_BRIDGE_MASK; - class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); + class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK; + class |= (PCI_CLASS_BRIDGE_PCI << 8); iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, class); -- 2.20.1