From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C80AFC433F5 for ; Wed, 5 Jan 2022 12:14:51 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 999BD83510; Wed, 5 Jan 2022 13:14:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8E2BA83681; Wed, 5 Jan 2022 13:14:47 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 135F183433 for ; Wed, 5 Jan 2022 13:14:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39F5E1FB; Wed, 5 Jan 2022 04:14:43 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B2753F5A1; Wed, 5 Jan 2022 04:14:40 -0800 (PST) Date: Wed, 5 Jan 2022 12:14:15 +0000 From: Andre Przywara To: Icenowy Zheng Cc: Jesse Taube , u-boot@lists.denx.de, jagan@amarulasolutions.com, hdegoede@redhat.com, sjg@chromium.org, marek.behun@nic.cz, festevam@denx.de, narmstrong@baylibre.com, tharvey@gateworks.com, christianshewitt@gmail.com, pbrobinson@gmail.com, lokeshvutla@ti.com, jernej.skrabec@gmail.com, hs@denx.de, samuel@sholland.org, arnaud.ferraris@gmail.com, giulio.benetti@benettiengineering.com, thirtythreeforty@gmail.com Subject: Re: [PATCH 00/11] Add support for SUNIV and F1C100s. Message-ID: <20220105121415.2df58be3@slackpad.fritz.box> In-Reply-To: <16f1b5aed8b616547084c64d2ec4398446681392.camel@aosc.io> References: <20220105003508.1143140-1-Mr.Bossman075@gmail.com> <16f1b5aed8b616547084c64d2ec4398446681392.camel@aosc.io> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Wed, 05 Jan 2022 19:36:29 +0800 Icenowy Zheng wrote: Hi Jesse, > =E5=9C=A8 2022-01-04=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 19:34 -0500=EF= =BC=8CJesse Taube=E5=86=99=E9=81=93=EF=BC=9A > > This patch set aims to add suport for the SUNIV and F1C100s. > > Suport has been in linux for a while now, but not in u-boot. > >=20 > > This patchset contains: > > - CPU specific initialization code > > - SUNIV dram driver > > - SUNIV clock driver adaption > > - SUNIV gpio driver adaption > > - SUNIV uart driver adaption > > - F1C100s basic support > >=20 > > I am hoping to get Icenowy's patches in as it seems she hasnt > > submitted > > in a while. The only edits I made to her code is rebasing it against > > ML > > and changing some formating. I also re-grouped her commits. =20 >=20 > I got too lazy to send it (because I think F1C100s is just too weak)... >=20 > >=20 > > I am wondering if the dram driver should be moved into device drivers > > rather than in mach-sunxi. > > I am also wondering if it is okay to submit some one elses code, > > and if so how should I do so. =20 >=20 > As you are keeping my SoB and adding yours, it's totally okay. Thanks Icenowy for confirming! Jesse: yes, it's perfectly fine to send patches from someone else, as long as you keep the authorship, their SoB, and add your's. Typical reasons are lack of time or interest from the original author. But it's customary to ask the author first, and care should be taken when changing patches, as this might not be in the interest of the original author (and they are the ones who will get blamed for bugs). Also please mark the series either as a Resend or as a v2. So with Icenowy's confirmation above I consider this fine. But what was actually holding back this series was lack of review, testing and/or interest. Similar to Icenowy my personal interest in crufty old cores is somewhat limited, so this wasn't very high on my priority list. So given that there is apparently some interest now: Can you confirm that you have reviewed the series, or at least tested this? I would be interested to know if a second pair of eyes had a look, and to what extent. I don't have any hardware, so would need to rely on others to make sure this code is somewhat sane. And it basically looks like a v2 of Icenowy's series, so can you give a Changelog of the differences? I skimmed over her original series back then, so I would be interested in what makes this version special. Cheers, Andre > Thanks for cleaning up these patches! ;-) >=20 > >=20 > > Icenowy Zheng (11): > > =C2=A0 arm: arm926ej-s: start.S: port save_boot_params support from arm= v7 > > =C2=A0=C2=A0=C2=A0 code > > =C2=A0 arm: arm926ej-s: add sunxi code > > =C2=A0 dt-bindings: clock: Add initial suniv headers > > =C2=A0 dt-bindings: reset: Add initial suniv headers > > =C2=A0 ARM: sunxi: Add support for F1C100s > > =C2=A0 sunxi: Add F1C100s DRAM initial support > > =C2=A0 sunxi: board: Add support for SUNIV > > =C2=A0 configs: sunxi: Add common SUNIV header > > =C2=A0 sunxi: Add support for SUNIV architecture > > =C2=A0 ARM: dts: suniv: Add device tree files for F1C100s > > =C2=A0 configs: sunxi: Add support for Lichee Pi Nano > >=20 > > =C2=A0arch/arm/cpu/arm926ejs/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > > =C2=A0arch/arm/cpu/arm926ejs/start.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 19 + > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 15 + > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/config.mk=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0=C2=A0 6 + > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/fel_utils.S=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 37 ++ > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S=C2=A0 |=C2=A0 67 +++ > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/start.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/timer.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 | 114 +++++ > > =C2=A0arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds=C2=A0=C2=A0 |=C2=A0 6= 2 +++ > > =C2=A0arch/arm/dts/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 + > > =C2=A0arch/arm/dts/suniv-f1c100s-licheepi-nano.dts=C2=A0 |=C2=A0 64 +++ > > =C2=A0arch/arm/dts/suniv-f1c100s.dtsi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 6 + > > =C2=A0arch/arm/dts/suniv.dtsi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 | 224 ++++++++++ > > =C2=A0arch/arm/include/asm/arch-sunxi/clock.h=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0=C2=A0 2 +- > > =C2=A0arch/arm/include/asm/arch-sunxi/clock_sun6i.h |=C2=A0 25 ++ > > =C2=A0arch/arm/include/asm/arch-sunxi/cpu_sun4i.h=C2=A0=C2=A0 |=C2=A0= =C2=A0 8 + > > =C2=A0arch/arm/include/asm/arch-sunxi/dram.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 + > > =C2=A0arch/arm/include/asm/arch-sunxi/dram_suniv.h=C2=A0 |=C2=A0 46 ++ > > =C2=A0arch/arm/include/asm/arch-sunxi/gpio.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > > =C2=A0arch/arm/mach-sunxi/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0 16 +- > > =C2=A0arch/arm/mach-sunxi/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0= =C2=A0 2 + > > =C2=A0arch/arm/mach-sunxi/board.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0 31 +- > > =C2=A0arch/arm/mach-sunxi/clock.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0 3 +- > > =C2=A0arch/arm/mach-sunxi/clock_sun6i.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 46 +- > > =C2=A0arch/arm/mach-sunxi/cpu_info.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 + > > =C2=A0arch/arm/mach-sunxi/dram_helpers.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 4 + > > =C2=A0arch/arm/mach-sunxi/dram_suniv.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 420 > > ++++++++++++++++++ > > =C2=A0board/sunxi/board.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 4 +- > > =C2=A0configs/licheepi_nano_defconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 13 + > > =C2=A0configs/licheepi_nano_spiflash_defconfig=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 25 ++ > > =C2=A0include/configs/suniv.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0 14 + > > =C2=A0include/configs/sunxi-common.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 67 ++- > > =C2=A0include/dt-bindings/clock/suniv-ccu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 68 +++ > > =C2=A0include/dt-bindings/reset/suniv-ccu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 36 ++ > > =C2=A034 files changed, 1424 insertions(+), 29 deletions(-) > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c > > =C2=A0create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds > > =C2=A0create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > > =C2=A0create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi > > =C2=A0create mode 100644 arch/arm/dts/suniv.dtsi > > =C2=A0create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h > > =C2=A0create mode 100644 arch/arm/mach-sunxi/dram_suniv.c > > =C2=A0create mode 100644 configs/licheepi_nano_defconfig > > =C2=A0create mode 100644 configs/licheepi_nano_spiflash_defconfig > > =C2=A0create mode 100644 include/configs/suniv.h > > =C2=A0create mode 100644 include/dt-bindings/clock/suniv-ccu.h > > =C2=A0create mode 100644 include/dt-bindings/reset/suniv-ccu.h > > =20 >=20 >=20