From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9466C433EF for ; Fri, 7 Jan 2022 17:27:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CA2A283747; Fri, 7 Jan 2022 18:27:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="BxEhUSxE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9DA14812C3; Fri, 7 Jan 2022 18:27:24 +0100 (CET) Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C85D383741 for ; Fri, 7 Jan 2022 18:27:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@amarulasolutions.com Received: by mail-wr1-x432.google.com with SMTP id k18so12318883wrg.11 for ; Fri, 07 Jan 2022 09:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Lo+cov+Y7Vn6xKGII3Y8qMxQCFy7yr72sIk7FEelCl4=; b=BxEhUSxE+MFUZ8JE54DB9UTRHi0A/5c7cM3MlN6C0+8qM0w4l7E7tC5OOYRkPTybfB OPqknIkAMG9QlvzEayNQotaJEleLHg4b0XGvl4CKUEfetNl9/+j6J7T2FQOH1dYPTLxb dMFH3/9wkpoMCgeVpPK1/Np5sZIKfxsW8aaZQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Lo+cov+Y7Vn6xKGII3Y8qMxQCFy7yr72sIk7FEelCl4=; b=KrpQgQ05Q9nojI/aUFMHBLQOwtCiEFicMM2EWZD8OTotSA3yZe7YOTh4kuHwTPW8ty 2g5rROQNrnPQ3GJegYT2ISDDLqAcqFXbgZKMcVo95tbc72ztx1vGQve/Q2u3sSCDlsNG 61dM4TOI0VwrowXh0xMJSbnpv40yG4kSC6KLUZDFOLSHJ3u2bK4zukbPjfjNOS1hwqEQ W6ZrJ45cnlpDUR+I6p0Qyd8HOyFp1JjGSJ3PZBCV/njmpDYx5FoErQjtpf9YJx/zhbTr Tq8YjW2rpwuBx9IMU2SUI+Pk8AqKAhPYuowswDZQTRoZthSzAmxpUA/cfXDxg2ZFZf3t XTag== X-Gm-Message-State: AOAM530f9pTVJ/rv8OCW682MJrzR5/s8tR6KBfwr3ONwYqo5DwK91rlW Nz56pPqZUpnAbbHwtMeM3DPKpg== X-Google-Smtp-Source: ABdhPJzHEWBmBNS1GGVU9xmK4avnyd+eKu/XwGyAJQh75p3M/yrqGSAXbaqKENP7rkTOeEZtRz4ERg== X-Received: by 2002:adf:a1d0:: with SMTP id v16mr9176002wrv.622.1641576440226; Fri, 07 Jan 2022 09:27:20 -0800 (PST) Received: from panicking.amarulasolutions.com ([2.197.88.79]) by smtp.gmail.com with ESMTPSA id 14sm5672147wry.23.2022.01.07.09.27.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 09:27:19 -0800 (PST) From: Michael Trimarchi To: Stefano Babic , Fabio Estevam Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Han Xu , Ye Li Subject: [PATCH V3] cmd_nandbcb: Support secondary boot address of imx8mn Date: Fri, 7 Jan 2022 18:27:17 +0100 Message-Id: <20220107172717.141051-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add support of secondary boot address for imx8mn. The secondary boot address is hardcoded in the fuse. The value is calculated from there according to the following description: The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows: - Secondary boot is disabled if fuse value is bigger than 10, n = fuse value bigger than 10. - n == 0: Offset = 4MB - n == 2: Offset = 1MB - Others & n <= 10 : Offset = 1MB*2^n - For FlexSPI boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7. Signed-off-by: Michael Trimarchi --- Changes V2->V3: Fix HECK: Unnecessary parentheses around 'plat_config.misc_flags' #162: FILE: arch/arm/mach-imx/cmd_nandbcb.c:1540: + if ((plat_config.misc_flags) & FIRMWARE_SECONDARY_FIXED_ADDR) { Changes V1->V2: - adjust commit message - drop and extra blank line --- arch/arm/mach-imx/cmd_nandbcb.c | 40 +++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 09622c13c9..fb4c59dd74 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -132,6 +132,7 @@ static struct platform_config imx8q_plat_config = { /* boot search related variables and definitions */ static int g_boot_search_count = 4; +static int g_boot_secondary_offset; static int g_boot_search_stride; static int g_pages_per_stride; @@ -275,9 +276,9 @@ static int nandbcb_set_boot_config(int argc, char * const argv[], boot_stream2_address = ((maxsize - boot_stream1_address) / 2 + boot_stream1_address); - if (boot_cfg->secondary_boot_stream_off_in_MB) + if (g_boot_secondary_offset) boot_stream2_address = - (loff_t)boot_cfg->secondary_boot_stream_off_in_MB * 1024 * 1024; + (loff_t)g_boot_secondary_offset * 1024 * 1024; max_boot_stream_size = boot_stream2_address - boot_stream1_address; @@ -1269,6 +1270,36 @@ static bool check_fingerprint(void *data, int fingerprint) return (*(int *)(data + off) == fingerprint); } +static int fuse_secondary_boot(u32 bank, u32 word, u32 mask, u32 off) +{ + int err; + u32 val; + int ret; + + err = fuse_read(bank, word, &val); + if (err) + return 0; + + val = (val & mask) >> off; + + if (val > 10) + return 0; + + switch (val) { + case 0: + ret = 4; + break; + case 1: + ret = 1; + break; + default: + ret = 2 << val; + break; + } + + return ret; +}; + static int fuse_to_search_count(u32 bank, u32 word, u32 mask, u32 off) { int err; @@ -1506,6 +1537,11 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc, g_boot_search_count); } + if (plat_config.misc_flags & FIRMWARE_SECONDARY_FIXED_ADDR) { + if (is_imx8mn()) + g_boot_secondary_offset = fuse_secondary_boot(2, 1, 0xff0000, 16); + } + cmd = argv[1]; --argc; ++argv; -- 2.25.1