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From: Johan Jonker <jbx6244@gmail.com>
To: kever.yang@rock-chips.com
Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, peng.fan@nxp.com,
	jh80.chung@samsung.com, u-boot@lists.denx.de
Subject: [PATCH v1 1/2] rockchip: mmc: rockchip_dw_mmc: fix ciu clock index
Date: Fri,  7 Jan 2022 19:34:05 +0100	[thread overview]
Message-ID: <20220107183406.1804-1-jbx6244@gmail.com> (raw)

The document rockchip-dw-mshc.yaml decribes a maximum of 4 clocks.
In the rockchip_dw_mmc driver the clock name in use was "fixed"
to "ciu" with index 1, but later reverted back to index 0.
The clock drivers can handle both, but the calling driver
should submit correct data as a standard practice.
Fix the "ciu" clock index by setting it back to 1.

  clock-names:
    minItems: 2
    items:
      - const: biu
      - const: ciu
      - const: ciu-drive
      - const: ciu-sample

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 drivers/mmc/rockchip_dw_mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 7f8dea1e..be065ec0 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -123,11 +123,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	priv->minmax[0] = 400000;  /*  400 kHz */
 	priv->minmax[1] = dtplat->max_frequency;
 
-	ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
+	ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
 	if (ret < 0)
 		return ret;
 #else
-	ret = clk_get_by_index(dev, 0, &priv->clk);
+	ret = clk_get_by_index(dev, 1, &priv->clk);
 	if (ret < 0)
 		return ret;
 #endif
-- 
2.20.1


             reply	other threads:[~2022-01-07 18:34 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-07 18:34 Johan Jonker [this message]
2022-01-07 18:34 ` [PATCH v1 2/2] rockchip: mmc: rockchip_dw_mmc: add rk3066/rk3188 support Johan Jonker
2022-03-12  9:02   ` Jagan Teki
2022-03-12  9:14     ` Johan Jonker

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