From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE436C433F5 for ; Sun, 9 Jan 2022 21:32:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3771B805F9; Sun, 9 Jan 2022 22:32:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A58EF80F78; Sun, 9 Jan 2022 22:32:32 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id D66C280562 for ; Sun, 9 Jan 2022 22:32:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1FA99ED1; Sun, 9 Jan 2022 13:32:27 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 735E33F5A1; Sun, 9 Jan 2022 13:32:25 -0800 (PST) Date: Sun, 9 Jan 2022 21:31:47 +0000 From: Andre Przywara To: Heinrich Schuchardt Cc: Tom Rini , Simon Glass , Alison Wang , Michael Walle , Nishanth Menon , Priyanka Singh , Peter Hoyes , Marek Vasut , u-boot@lists.denx.de Subject: Re: [PATCH 1/6] cmd: exception: arm64: fix undefined, add faults Message-ID: <20220109213147.479dad13@slackpad.fritz.box> In-Reply-To: <7fd24059-c47a-b7ec-3ecb-7066e33fcdc1@canonical.com> References: <20220109173009.25522-1-andre.przywara@arm.com> <20220109173009.25522-2-andre.przywara@arm.com> <7fd24059-c47a-b7ec-3ecb-7066e33fcdc1@canonical.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Sun, 9 Jan 2022 20:08:41 +0100 Heinrich Schuchardt wrote: > On 1/9/22 18:30, Andre Przywara wrote: > > The arm64 version of the exception command was just defining the > > undefined exception, but actually copied the AArch32 instruction. > > > > Replace that with an encoding that is guaranteed to be and stay > > undefined. Also add instructions to trigger unaligned access faults and > > a breakpoint. > > This brings ARM64 on par with ARM(32) for the exception command. > > > > Signed-off-by: Andre Przywara > > --- > > cmd/arm/exception64.c | 42 ++++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 38 insertions(+), 4 deletions(-) > > > > diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c > > index d5de50a0803..1a9730e6aec 100644 > > --- a/cmd/arm/exception64.c > > +++ b/cmd/arm/exception64.c > > @@ -12,14 +12,46 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, > > char *const argv[]) > > { > > /* > > - * 0xe7f...f. is undefined in ARM mode > > - * 0xde.. is undefined in Thumb mode > > + * Instructions starting with the upper 16 bits all 0 are permanently > > + * undefined. The lower 16 bits can be used for some kind of immediate. > > + * --- ARMv8 ARM (ARM DDI 0487G.a C6.2.339: "UDF") > > */ > > - asm volatile (".word 0xe7f7defb\n"); > > + asm volatile (".word 0x00001234\n"); > > + > > + return CMD_RET_FAILURE; > > +} > > + > > +static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, > > + char *const argv[]) > > +{ > > + /* > > + * The load acquire instruction requires the data source to be > > + * naturally aligned, and will fault even if strict alignment fault > > + * checking is disabled. > > + * --- ARMv8 ARM (ARM DDI 0487G.a B2.5.2: "Alignment of data accesses") > > According to DI0487G_b_armv8_arm.pdf available at > https://developer.arm.com/documentation/ddi0487/latest the generation of > an alignment fault for ldar depends on FEAT_LSE2 (Large System > Extensions v2) which is mandatory for ARMv8.4. See p. B2-161. Well found, but I wonder if that matters for the SoCs running U-Boot. It looks like the Apple M1 is the only one so far and will probably stay for a while. But I can of course check ID_AA64MMFR2_EL1.AT before executing the LDAR, and will ask around for a better method to provoke unaligned accesses. Cheers, Andre > > Best regards > > Heinrich > > > + */ > > + asm volatile ( > > + "mov x1, sp\n\t" > > + "orr x1, x1, #3\n\t" > > + "ldar x0, [x1]\n" > > + ::: "x0", "x1" ); > > + > > + return CMD_RET_FAILURE; > > +} > > + > > +static int do_breakpoint(struct cmd_tbl *cmdtp, int flag, int argc, > > + char *const argv[]) > > +{ > > + asm volatile ("brk #123\n"); > > + > > return CMD_RET_FAILURE; > > } > > > > static struct cmd_tbl cmd_sub[] = { > > + U_BOOT_CMD_MKENT(breakpoint, CONFIG_SYS_MAXARGS, 1, do_breakpoint, > > + "", ""), > > + U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, > > + "", ""), > > U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, > > "", ""), > > }; > > @@ -27,7 +59,9 @@ static struct cmd_tbl cmd_sub[] = { > > static char exception_help_text[] = > > "\n" > > " The following exceptions are available:\n" > > - " undefined - undefined instruction\n" > > + " breakpoint - breakpoint instruction exception\n" > > + " unaligned - unaligned LDAR data abort\n" > > + " undefined - undefined instruction exception\n" > > ; > > > > #include