From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E84BBC433F5 for ; Tue, 11 Jan 2022 12:46:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CDE60830A1; Tue, 11 Jan 2022 13:46:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id C0FDA830A1; Tue, 11 Jan 2022 13:46:18 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id E605283025 for ; Tue, 11 Jan 2022 13:46:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 617A6ED1; Tue, 11 Jan 2022 04:46:14 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AAF233F774; Tue, 11 Jan 2022 04:46:12 -0800 (PST) From: Andre Przywara To: Jagan Teki Cc: Simon Glass , Tom Rini , Chen-Yu Tsai , Hauke Mehrtens , Jernej Skrabec , Samuel Holland , Icenowy Zheng , Joe Hershberger , Wolfgang Denk , Daniel Wagenknecht , u-boot@lists.denx.de Subject: [PATCH 1/7] sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs Date: Tue, 11 Jan 2022 12:46:01 +0000 Message-Id: <20220111124607.863952-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220111124607.863952-1-andre.przywara@arm.com> References: <20220111124607.863952-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Daniel Wagenknecht The driver for SPI0 on Allwinner H6 SoCs did not use the correct define SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner SoC series. Fix the conditionals to use the correct define for H6 SoCs. This matches the conditional logic in the SPL spi driver. Tested by probing the spi-flash on a pine64_h64-model-b board with adapted device-tree (disable mmc2, enable spi0). Signed-off-by: Daniel Wagenknecht Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/spi/spi-sunxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index bc2f544e86..d62355ec6f 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -249,7 +249,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev) if (pin < 0) break; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0); else sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); -- 2.25.1