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[2603:6081:7b01:cbda:9533:c51:a891:732b]) by smtp.gmail.com with ESMTPSA id q27sm3764114qki.100.2022.01.14.10.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jan 2022 10:17:24 -0800 (PST) Date: Fri, 14 Jan 2022 13:17:23 -0500 From: Tom Rini To: AJ Bagwell Cc: u-boot@lists.denx.de, AJ Bagwell Subject: Re: [PATCH] pinctrl: single: add support for pinctrl-single, pins when #pinctrl-cells = 2 Message-ID: <20220114181723.GA1811065@bill-the-cat> References: <20211203151853.97970-1-anthony.bagwell@hivehome.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="G4iJoqBmSsgzjUCe" Content-Disposition: inline In-Reply-To: <20211203151853.97970-1-anthony.bagwell@hivehome.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean --G4iJoqBmSsgzjUCe Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Dec 03, 2021 at 03:18:53PM +0000, AJ Bagwell wrote: > Changes to the am33xx device (33e9021a) trees have been merged in from > the upstream linux kernel which now means the device tree uses the new > pins format (as of 5.10) where the confinguration can be stores as a > separate configuration value and pin mux mode which are then OR'd > together. >=20 > This patch adds support for the new format to u-boot so that > pinctrl-cells is now respected when reading in pinctrl-single,pins > --- > drivers/pinctrl/pinctrl-single.c | 55 +++++++++++++++++--------------- > 1 file changed, 29 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-s= ingle.c > index 8fc07e3498..bc9c17bce8 100644 > --- a/drivers/pinctrl/pinctrl-single.c > +++ b/drivers/pinctrl/pinctrl-single.c > @@ -28,6 +28,7 @@ struct single_pdata { > int offset; > u32 mask; > u32 width; > + u32 args_count; > bool bits_per_mux; > }; > =20 > @@ -78,20 +79,6 @@ struct single_priv { > struct list_head gpiofuncs; > }; > =20 > -/** > - * struct single_fdt_pin_cfg - pin configuration > - * > - * This structure is used for the pin configuration parameters in case > - * the register controls only one pin. > - * > - * @reg: configuration register offset > - * @val: configuration register value > - */ > -struct single_fdt_pin_cfg { > - fdt32_t reg; > - fdt32_t val; > -}; > - > /** > * struct single_fdt_bits_cfg - pin configuration > * > @@ -314,25 +301,28 @@ static int single_pin_compare(const void *s1, const= void *s2) > * @dev: Pointer to single pin configuration device which is the parent = of > * the pins node holding the pin configuration data. > * @pins: Pointer to the first element of an array of register/value pai= rs > - * of type 'struct single_fdt_pin_cfg'. Each such pair describes = the > - * the pin to be configured and the value to be used for configur= ation. > + * of type 'u32'. Each such pair describes the pin to be configur= ed=20 > + * and the value to be used for configuration. > + * The value can either be a simple value if #pinctrl-cells =3D 1 > + * or a configuration value and a pin mux mode value if it is 2 > * This pointer points to a 'pinctrl-single,pins' property in the > * device-tree. > * @size: Size of the 'pins' array in bytes. > - * The number of register/value pairs in the 'pins' array therefo= re > - * equals to 'size / sizeof(struct single_fdt_pin_cfg)'. > + * The number of cells in the array therefore equals to > + * 'size / sizeof(u32)'. > * @fname: Function name. > */ > static int single_configure_pins(struct udevice *dev, > - const struct single_fdt_pin_cfg *pins, > + const u32 *pins, > int size, const char *fname) > { > struct single_pdata *pdata =3D dev_get_plat(dev); > struct single_priv *priv =3D dev_get_priv(dev); > - int n, pin, count =3D size / sizeof(struct single_fdt_pin_cfg); > + int stride =3D pdata->args_count + 1; > + int n, pin, count =3D size / sizeof(u32); > struct single_func *func; > phys_addr_t reg; > - u32 offset, val; > + u32 offset, val, mux; > =20 > /* If function mask is null, needn't enable it. */ > if (!pdata->mask) > @@ -344,16 +334,22 @@ static int single_configure_pins(struct udevice *de= v, > =20 > func->name =3D fname; > func->npins =3D 0; > - for (n =3D 0; n < count; n++, pins++) { > - offset =3D fdt32_to_cpu(pins->reg); > + for (n =3D 0; n < count; n +=3D stride) { > + offset =3D fdt32_to_cpu(pins[n]); > if (offset > pdata->offset) { > dev_err(dev, " invalid register offset 0x%x\n", > offset); > continue; > } > =20 > + /* if the pinctrl-cells is 2 then the second cell contains the mux */ > + if (stride =3D=3D 3) > + mux =3D fdt32_to_cpu(pins[n + 2]); > + else > + mux =3D 0; > + > reg =3D pdata->base + offset; > - val =3D fdt32_to_cpu(pins->val) & pdata->mask; > + val =3D (fdt32_to_cpu(pins[n + 1]) | mux) & pdata->mask; > pin =3D single_get_pin_by_offset(dev, offset); > if (pin < 0) { > dev_err(dev, " failed to get pin by offset %x\n", > @@ -453,7 +449,7 @@ static int single_configure_bits(struct udevice *dev, > static int single_set_state(struct udevice *dev, > struct udevice *config) > { > - const struct single_fdt_pin_cfg *prop; > + const u32 *prop; > const struct single_fdt_bits_cfg *prop_bits; > int len; > =20 > @@ -461,7 +457,7 @@ static int single_set_state(struct udevice *dev, > =20 > if (prop) { > dev_dbg(dev, "configuring pins for %s\n", config->name); > - if (len % sizeof(struct single_fdt_pin_cfg)) { > + if (len % sizeof(u32)) { > dev_dbg(dev, " invalid pin configuration in fdt\n"); > return -FDT_ERR_BADSTRUCTURE; > } > @@ -612,6 +608,13 @@ static int single_of_to_plat(struct udevice *dev) > =20 > pdata->bits_per_mux =3D dev_read_bool(dev, "pinctrl-single,bit-per-mux"= ); > =20 > + /* If no pinctrl-cells is present, default to old style of 2 cells with > + * bits per mux and 1 cell otherwise. > + */ > + ret =3D dev_read_u32(dev, "#pinctrl-cells", &pdata->args_count); > + if (ret) > + pdata->args_count =3D pdata->bits_per_mux ? 2 : 1; > + > return 0; > } While this change seems fine, it is missing a Signed-off-by line. Please see https://developercertificate.org/ and if so, either repost or reply with your line here as the change otherwise still applies fine, thanks. --=20 Tom --G4iJoqBmSsgzjUCe Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmHhvjMACgkQFHw5/5Y0 tyzEzwv/S+DAe00CSbPdhXPzFcrjk3HRLUOnsTymXw6lto86MqI/5lS42vki7LD2 J1l62pl9Tmui3lD4iiJKKq143VpmxcSSYgwe6zcn14g7BdfRdYvgvXt1Y0QhD8x5 id5cI1KF9zv+rZ7NeADZnxzJ28dWPvp+1jfjSUi81XhO73fkIiUyI29omGRRKvyH o57YMwlMLM5gKd6VyQDwejTTJULe82Vj2dMhv80IiIqzG3vg9dmKIa5v1x70+x9x W3Toz/EmLQeE3D2iy/OLrulEF4Boq6GGsLoKcaKXVT0A3avgyj38rK1QxOe4yrBa wW1V2GX5XC//hIXIzCx+mkxF3AakHfso5hnWXk9OxHhHhTk3VyRiMvXeXVIGvE0d uY8mIcMhCaLUa7GCquAQWgV/XhIQgAMslTreiu+0KzBWxyYU24XmUkXzp4HG2KAs Kc+YGT261enjZSI4l+TdBoUCtkHEEmRQQV7/D6DxFRx/D1cXvgieoc5J6vgkmZUA /A8O0G4I =ZqB8 -----END PGP SIGNATURE----- --G4iJoqBmSsgzjUCe--