From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8652C433EF for ; Tue, 18 Jan 2022 00:38:16 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A530683841; Tue, 18 Jan 2022 01:37:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hFbUXQoX"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1317D83815; Tue, 18 Jan 2022 01:37:30 +0100 (CET) Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 60240837FD for ; Tue, 18 Jan 2022 01:37:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jbx6244@gmail.com Received: by mail-ed1-x531.google.com with SMTP id k15so72307056edk.13 for ; Mon, 17 Jan 2022 16:37:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UnB712SDOwzAeGV6iUa46WGmd2LHA16F7VVzXxBhJac=; b=hFbUXQoXL0I4Bg6z27NzTSyTC6yhXS5wKh9gJS7CsM0dlEIpILYfPBPmt22jCTuviA l/etWa9zQZDMB0jccorITYjkkv2bX6Q/pjwIqIKdvjLoRv+TfJRZoBS29gJ+ttP6/JTz TpDPDyGpTCZ5jQtU+q9BiTC8E8JN4c2YicFDoWCkuRCovlfMk394I0LOiXgQR3gOSXZO b1BTEtn9Y2Lm9g0vRHQc2U4zTfhVpD5Z9cFUD1ssAYuUVKkCZ44Lk6qUUuSLRLz7BetX r1plu9x4fS9JuSexag/obLeupFHv7V30wCQ9hZ7Pzt/9s38bxziUDcDuqKfjTklk+kz2 ditQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UnB712SDOwzAeGV6iUa46WGmd2LHA16F7VVzXxBhJac=; b=z9vhZ+mJMZJ+/0/xJ0e9ZlgQpOddkX8IX4BeCkirLQ5O4VG/FS2p3oevGTfeAHUSFI 0sfjSCQhKktRyP4P9gjJh4R9zdolUyn0DI4dSgyyfZgfRrQYXbC3DL+WVW8Ljq9zj8LU tZKVGhO7DwAfrv5CYmnbhrmnrLhCUUIvS9gB1bM+UUqRfhnAdQVmvtUZg202TwB+nnhB O2uDG7FKIAtYQehowe/kTbr4frTl0fvoLkoYq7WDcAqOqorETNKrxXf7JI07bqzz2w/i Man1uGHD4TB42shhEMqmXhQBQLdJwqLzDE2cRfaJidLPPkCLsBA0O/+qIT01TetGI4Uq Usjw== X-Gm-Message-State: AOAM533GMTie8E9qeo51w2USSM/V6add6qYGbJCBhlOiPtp09faapn1I JKO9Kw4bolp08m41qmPOtXk= X-Google-Smtp-Source: ABdhPJwZcKmtf7dxf9KCUQWniafMu8u58fm+y9GrYYDJWFa/YaafwXvcSLu1gdSZFfFO+or0dqDARQ== X-Received: by 2002:a05:6402:26c5:: with SMTP id x5mr1896480edd.22.1642466238010; Mon, 17 Jan 2022 16:37:18 -0800 (PST) Received: from debian.home ([81.204.249.205]) by smtp.gmail.com with ESMTPSA id bg20sm4312606ejb.59.2022.01.17.16.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 16:37:17 -0800 (PST) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, lukma@denx.de, seanga2@gmail.com, u-boot@lists.denx.de Subject: [PATCH v8 04/15] rockchip: rk3066: add rk3066 pinctrl driver Date: Tue, 18 Jan 2022 01:36:52 +0100 Message-Id: <20220118003703.10678-5-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220118003703.10678-1-jbx6244@gmail.com> References: <20220118003703.10678-1-jbx6244@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: PaweÅ‚ Jarosz Add driver supporting pin multiplexing on rk3066 platform. Signed-off-by: PaweÅ‚ Jarosz Signed-off-by: Johan Jonker --- Changed V7: restyle changed function prefix. restyle U_BOOT_DRIVER structure use OF_REAL use EOPNOTSUPP --- drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rk3066.c | 113 ++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index fcf19f87..7d03f810 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-rockchip-core.o obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c new file mode 100644 index 00000000..c329dd45 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-rockchip.h" + +static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RK3066_PULL_OFFSET 0x118 +#define RK3066_PULL_PINS_PER_REG 16 +#define RK3066_PULL_BANK_STRIDE 8 + +static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3066_PULL_OFFSET; + *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE; + *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4; + + *bit = pin_num % RK3066_PULL_PINS_PER_REG; +}; + +static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -EOPNOTSUPP; + + rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +static struct rockchip_pin_bank rk3066_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), + PIN_BANK(4, 32, "gpio4"), + PIN_BANK(6, 16, "gpio6"), +}; + +static struct rockchip_pin_ctrl rk3066_pin_ctrl = { + .pin_banks = rk3066_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066_pin_banks), + .grf_mux_offset = 0xa8, + .set_mux = rk3066_pinctrl_set_mux, + .set_pull = rk3066_pinctrl_set_pull, +}; + +static const struct udevice_id rk3066_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3066a-pinctrl", + .data = (ulong)&rk3066_pin_ctrl + }, + {} +}; + +U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = { + .name = "rockchip_rk3066a_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &rockchip_pinctrl_ops, + .probe = rockchip_pinctrl_probe, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .of_match = rk3066_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), +}; -- 2.20.1