From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CFDCC433EF for ; Tue, 25 Jan 2022 02:49:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4E254835EA; Tue, 25 Jan 2022 03:49:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1643078945; bh=SI0W9JksMz/4g0uOVs5pgf2JikBmxOlo6Xhs9ytJxlM=; h=From:To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=i3ZRYaTU8Lyp8YLWIPmemSeN8Pa7mMQJD+8zjFJHgIcZ91Fwb2iBxfo1DZ2KbB3/3 3ylU6n70j8lbj5mdsQZPMK9de/+3kwujkrwgT8K7/sebnIeaCV5GLxLsCyJZpO+bhZ ou19bLT2glo0N9xrQJKF+P5piFm6ezSdctYnnBJvQ9rWBE+bybR8JKGXpXaAgPPS/4 e8H98na48TgFmaLh40qsFK2byq3ANSovKZQi8SadH9EzV7MblVw7t6d5YuD4mDnxXy 0oNGY8BIE5QJJ+v+alz8pBwRLvxvlGfBEc8kR5kV37aBYYhsdvKpybuUWWsL9/T5s3 yXNmyrKsSMLSw== Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 3D7D7834CF; Tue, 25 Jan 2022 03:49:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1643078941; bh=SI0W9JksMz/4g0uOVs5pgf2JikBmxOlo6Xhs9ytJxlM=; h=From:To:Cc:Subject:Date:From; b=hCXQziB0xCkRwT23YNIc8dJChzZgdWnl3yKwY9Shloq1w0841yBBYC+sLUyXXyUGj ndoKifPVSsHGxs+OnWkYH/mQOgu3zqIhiDlvm85uRdtFu3eB9GujJxp9md/1a6GK52 ZgKMcU7Gk4JD7b7wWmjiI4Oa/0xOWcPIQRNBlzAnHAKjkyw+ddnsvd68e7gFRnh/gB zN9tTAKUrnkyx8s/rfTsZ6jFO3OwojB/yvQEwUzjeVNGgiZOOoJW4V921f28uSdrHQ Meo+c4QZkec69pHXf9q9nY8LR7jHAGC75uAMKLh5RhyvmM1mjkR23Aq5CKbjJisYjs 0fi9rVAqcZqJg== From: Marek Vasut To: u-boot@lists.denx.de Cc: sbabic@denx.de, =?UTF-8?q?Oliver=20St=C3=A4bler?= , Fabio Estevam , Rob Herring , Shawn Guo , Marek Vasut Subject: [PATCH] arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0 Date: Tue, 25 Jan 2022 03:48:54 +0100 Message-Id: <20220125024854.129697-1-marex@denx.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Oliver Stäbler Fix address of the pad control register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems to be a typo but it leads to an exception when pinctrl is applied due to wrong memory address access. Signed-off-by: Oliver Stäbler Reviewed-by: Fabio Estevam Acked-by: Rob Herring Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm") Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ") Signed-off-by: Shawn Guo Signed-off-by: Marek Vasut # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0") --- arch/arm/dts/imx8mm-pinfunc.h | 2 +- arch/arm/dts/imx8mq-pinfunc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h index 5ccc4cc9195..a003e6af335 100644 --- a/arch/arm/dts/imx8mm-pinfunc.h +++ b/arch/arm/dts/imx8mm-pinfunc.h @@ -124,7 +124,7 @@ #define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h index b94b02080a3..68e8fa17297 100644 --- a/arch/arm/dts/imx8mq-pinfunc.h +++ b/arch/arm/dts/imx8mq-pinfunc.h @@ -130,7 +130,7 @@ #define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -- 2.34.1