From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43B1EC433EF for ; Thu, 27 Jan 2022 06:11:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CA58B82FA5; Thu, 27 Jan 2022 07:11:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="AE3ZqVM7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6239F82F8E; Thu, 27 Jan 2022 07:11:44 +0100 (CET) Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EC13980F3F for ; Thu, 27 Jan 2022 07:11:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=apatel@ventanamicro.com Received: by mail-pg1-x52a.google.com with SMTP id f8so1386253pgf.8 for ; Wed, 26 Jan 2022 22:11:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y9iWtOvikYCr8kLLVg7vODksNwsIac3hqb21lVuBQ4E=; b=AE3ZqVM78L5+nS/n39kya6L4A2sUuU3sCV+2KQSInHIFHzEbn1LeIv8WnN2/0THciS 3kBHaiWrA6nJBrUrWQquBcVrZljD6RfLORxBMOpHeMHWHXLzk2AREBgGf75XcyDfdQmm TD14Ug/Y/Howm1HJTP8TkUQIkBi5Y7ZgDO3LZYy4RI4X1IPXJmvRsVjlJUMPHMOuvWKE jnSVCRHKrN6QzPB+pyYkfejpLVoeZIAYAm47ZJ7UN9FinhNCarhT2QKEX0ryPqkGqu/E cSuk8KP/RPEjcDd3unPmTkIK9nLitSNGuxPgc9zwdgc3JXzCbo9afhU9aAcBlRLkwg+r HGIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y9iWtOvikYCr8kLLVg7vODksNwsIac3hqb21lVuBQ4E=; b=BynyFOIXuIJzR95CZWxdO+zRRHg4PP3tY9LDTa2vLPVgn9NqiOwfhZBr5Of5Ghs2sf rKOAo5pAz0C4HEb4Bnvunc8PkoC2Dh7JKOPo23pg4j2bSfvxNdOuVXOc1tM6OKT3M9Gw QNB5gLluIrCAJP23l0E0zycTI+dsS88+n812s3gjbjOdRtFYpbAf9lRPVr8TeT4x6fzh /9tbjokLU/RzD+yFEcDd0qTqqxIg7pAAKGA/0YGesIhmWKm15F8phK/1mFxUe783w9dL HezwdMSBStGqJY3uhtfrdt/r4uh+Hi5E8z03trmIUTVv9OzKnqJmxeujvJAt3UUX6JF6 df6A== X-Gm-Message-State: AOAM533d1vK9w9U5sRZc93eqhk0ErVFu7NVLR3k6U3eEwImo4kFsuCEN eDISfRKc0H9tVB9aoXSciy2NyA== X-Google-Smtp-Source: ABdhPJzeKBv7HczTAgho0+gT1N19PDkTziUF/DccyYx4xevoQdjoP/g1Fq2nO8Jk9mvJHNQNY/icJA== X-Received: by 2002:a05:6a00:803:: with SMTP id m3mr1657827pfk.60.1643263899158; Wed, 26 Jan 2022 22:11:39 -0800 (PST) Received: from localhost.localdomain ([171.61.74.240]) by smtp.gmail.com with ESMTPSA id j4sm4732441pjv.46.2022.01.26.22.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 22:11:38 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng Cc: Atish Patra , Alistair Francis , Anup Patel , U-Boot Mailing List , Anup Patel , Philipp Tomsich Subject: [PATCH v2 1/4] serial: Add RISC-V HTIF console driver Date: Thu, 27 Jan 2022 11:41:07 +0530 Message-Id: <20220127061110.721103-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127061110.721103-1-apatel@ventanamicro.com> References: <20220127061110.721103-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Quite a few RISC-V emulators and ISS (including Spike) have host transfer interface (HTIF) based console. This patch adds HTIF based console driver for RISC-V platforms which depends totally on DT node for HTIF register base address. Signed-off-by: Anup Patel Reviewed-by: Philipp Tomsich Reviewed-by: Rick Chen --- drivers/serial/Kconfig | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_htif.c | 178 +++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 drivers/serial/serial_htif.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6c8fdda9a0..345d1881f5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -866,6 +866,14 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config HTIF_CONSOLE + bool "RISC-V HTIF console support" + depends on DM_SERIAL && 64BIT + help + Select this to enable host transfer interface (HTIF) based serial + console. The HTIF device is quite common in RISC-V emulators and + RISC-V ISS so this driver allows using U-Boot on such platforms. + config SIFIVE_SERIAL bool "SiFive UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8168af640f..52e70aa191 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o +obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o obj-$(CONFIG_XEN_SERIAL) += serial_xen.o diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c new file mode 100644 index 0000000000..5d2bf0aaeb --- /dev/null +++ b/drivers/serial/serial_htif.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define HTIF_DATA_BITS 48 +#define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1) +#define HTIF_DATA_SHIFT 0 +#define HTIF_CMD_BITS 8 +#define HTIF_CMD_MASK ((1ULL << HTIF_CMD_BITS) - 1) +#define HTIF_CMD_SHIFT 48 +#define HTIF_DEV_BITS 8 +#define HTIF_DEV_MASK ((1ULL << HTIF_DEV_BITS) - 1) +#define HTIF_DEV_SHIFT 56 + +#define HTIF_DEV_SYSTEM 0 +#define HTIF_DEV_CONSOLE 1 + +#define HTIF_CONSOLE_CMD_GETC 0 +#define HTIF_CONSOLE_CMD_PUTC 1 + +#if __riscv_xlen == 64 +# define TOHOST_CMD(dev, cmd, payload) \ + (((u64)(dev) << HTIF_DEV_SHIFT) | \ + ((u64)(cmd) << HTIF_CMD_SHIFT) | \ + (u64)(payload)) +#else +# define TOHOST_CMD(dev, cmd, payload) ({ \ + if ((dev) || (cmd)) \ + __builtin_trap(); \ + (payload); }) +#endif +#define FROMHOST_DEV(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_DEV_SHIFT) & HTIF_DEV_MASK) +#define FROMHOST_CMD(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_CMD_SHIFT) & HTIF_CMD_MASK) +#define FROMHOST_DATA(fromhost_value) \ + ((u64)((fromhost_value) >> HTIF_DATA_SHIFT) & HTIF_DATA_MASK) + +struct htif_plat { + void *fromhost; + void *tohost; + int console_char; +}; + +static void __check_fromhost(struct htif_plat *plat) +{ + u64 fh = readq(plat->fromhost); + + if (!fh) + return; + writeq(0, plat->fromhost); + + /* this should be from the console */ + if (FROMHOST_DEV(fh) != HTIF_DEV_CONSOLE) + __builtin_trap(); + switch (FROMHOST_CMD(fh)) { + case HTIF_CONSOLE_CMD_GETC: + plat->console_char = 1 + (u8)FROMHOST_DATA(fh); + break; + case HTIF_CONSOLE_CMD_PUTC: + break; + default: + __builtin_trap(); + } +} + +static void __set_tohost(struct htif_plat *plat, + u64 dev, u64 cmd, u64 data) +{ + while (readq(plat->tohost)) + __check_fromhost(plat); + writeq(TOHOST_CMD(dev, cmd, data), plat->tohost); +} + +static int htif_serial_putc(struct udevice *dev, const char ch) +{ + struct htif_plat *plat = dev_get_plat(dev); + + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_PUTC, ch); + return 0; +} + +static int htif_serial_getc(struct udevice *dev) +{ + int ch; + struct htif_plat *plat = dev_get_plat(dev); + + if (plat->console_char < 0) + __check_fromhost(plat); + + if (plat->console_char >= 0) { + ch = plat->console_char; + plat->console_char = -1; + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0); + return (ch) ? ch - 1 : -EAGAIN; + } + + return -EAGAIN; +} + +static int htif_serial_pending(struct udevice *dev, bool input) +{ + struct htif_plat *plat = dev_get_plat(dev); + + if (!input) + return 0; + + if (plat->console_char < 0) + __check_fromhost(plat); + + return (plat->console_char >= 0) ? 1 : 0; +} + +static int htif_serial_probe(struct udevice *dev) +{ + struct htif_plat *plat = dev_get_plat(dev); + + /* Queue first getc request */ + __set_tohost(plat, HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0); + + return 0; +} + +static int htif_serial_of_to_plat(struct udevice *dev) +{ + fdt_addr_t addr; + struct htif_plat *plat = dev_get_plat(dev); + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + plat->fromhost = (void *)(uintptr_t)addr; + plat->tohost = plat->fromhost + sizeof(u64); + + addr = dev_read_addr_index(dev, 1); + if (addr != FDT_ADDR_T_NONE) + plat->tohost = (void *)(uintptr_t)addr; + + plat->console_char = -1; + + return 0; +} + +static const struct dm_serial_ops htif_serial_ops = { + .putc = htif_serial_putc, + .getc = htif_serial_getc, + .pending = htif_serial_pending, +}; + +static const struct udevice_id htif_serial_ids[] = { + { .compatible = "ucb,htif0" }, + { } +}; + +U_BOOT_DRIVER(serial_htif) = { + .name = "serial_htif", + .id = UCLASS_SERIAL, + .of_match = htif_serial_ids, + .of_to_plat = htif_serial_of_to_plat, + .plat_auto = sizeof(struct htif_plat), + .probe = htif_serial_probe, + .ops = &htif_serial_ops, +}; -- 2.25.1