From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB43EC433F5 for ; Fri, 28 Jan 2022 00:42:04 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ABA8E837CE; Fri, 28 Jan 2022 01:42:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1565A835F4; Fri, 28 Jan 2022 01:42:00 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 478E7837CE for ; Fri, 28 Jan 2022 01:41:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35E1211D4; Thu, 27 Jan 2022 16:41:55 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7DB053F793; Thu, 27 Jan 2022 16:41:52 -0800 (PST) Date: Fri, 28 Jan 2022 00:41:37 +0000 From: Andre Przywara To: Jesse Taube Cc: samuel@sholland.org, u-boot@lists.denx.de, jagan@amarulasolutions.com, hdegoede@redhat.com, sjg@chromium.org, icenowy@aosc.io, marek.behun@nic.cz, festevam@denx.de, narmstrong@baylibre.com, tharvey@gateworks.com, christianshewitt@gmail.com, pbrobinson@gmail.com, jernej.skrabec@gmail.com, hs@denx.de, arnaud.ferraris@gmail.com, giulio.benetti@benettiengineering.com, thirtythreeforty@gmail.com Subject: Re: [PATCH v2 02/12] mach-sunxi: Move timer code to mach folder Message-ID: <20220128004137.470fc71a@slackpad.fritz.box> In-Reply-To: <81d96db1-52e1-c7c4-3b00-1a9affa474dd@gmail.com> References: <20220126135329.2997430-1-Mr.Bossman075@gmail.com> <20220126135329.2997430-3-Mr.Bossman075@gmail.com> <20220127102114.13263dc4@donnerap.cambridge.arm.com> <81d96db1-52e1-c7c4-3b00-1a9affa474dd@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 27 Jan 2022 15:40:13 -0500 Jesse Taube wrote: Hi, > On 1/27/22 05:21, Andre Przywara wrote: > > On Wed, 26 Jan 2022 08:53:19 -0500 > > Jesse Taube wrote: > > > >> Both armv7 and arm926ejs use this timer code so move it to mach-sunxi. > > > > Very nice, thanks for cleaning this up. > > > > But please remove the respective line from the Makefile in > > arch/arm/cpu/armv7/sunxi/, otherwise 32-bit board builds fail: > > make[2]: *** No rule to make target 'arch/arm/cpu/armv7/sunxi/timer.o' ... > Oh my I'm very sorry about this. There is one thing though > arch/arm/cpu/armv7/sunxi/ needs to have one .o file in there to compile. > If I remove `ifdef CONFIG_SPL_BUILD` for fel_utils it will work but its > not used in u-boot proper. Mmh, not sure I follow, I cannot reproduce any problem. Can you elaborate? And did you do a "make clean" afterwards? Cheers, Andre > > Cheers, > > Andre > > > >> Signed-off-by: Jesse Taube > >> --- > >> V1->V2: > >> * New commit > >> --- > >> arch/arm/mach-sunxi/Makefile | 3 +++ > >> arch/arm/{cpu/armv7/sunxi => mach-sunxi}/timer.c | 7 ++++--- > >> 2 files changed, 7 insertions(+), 3 deletions(-) > >> rename arch/arm/{cpu/armv7/sunxi => mach-sunxi}/timer.c (97%) > >> > >> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile > >> index 5d3fd70f74..b1adb75e17 100644 > >> --- a/arch/arm/mach-sunxi/Makefile > >> +++ b/arch/arm/mach-sunxi/Makefile > >> @@ -25,6 +25,9 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o > >> endif > >> obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o > >> obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o > >> +ifndef CONFIG_ARM64 > >> +obj-y += timer.o > >> +endif > >> > >> ifdef CONFIG_SPL_BUILD > >> obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o > >> diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/mach-sunxi/timer.c > >> similarity index 97% > >> rename from arch/arm/cpu/armv7/sunxi/timer.c > >> rename to arch/arm/mach-sunxi/timer.c > >> index b758599636..fc9d419a25 100644 > >> --- a/arch/arm/cpu/armv7/sunxi/timer.c > >> +++ b/arch/arm/mach-sunxi/timer.c > >> @@ -51,6 +51,7 @@ int timer_init(void) > >> struct sunxi_timer_reg *timers = > >> (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; > >> struct sunxi_timer *timer = &timers->timer[TIMER_NUM]; > >> + > >> writel(TIMER_LOAD_VAL, &timer->inter); > >> writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN, > >> &timer->ctl); > >> @@ -58,15 +59,14 @@ int timer_init(void) > >> return 0; > >> } > >> > >> -/* timer without interrupts */ > >> static ulong get_timer_masked(void) > >> { > >> /* current tick value */ > >> ulong now = TICKS_TO_HZ(read_timer()); > >> > >> - if (now >= gd->arch.lastinc) /* normal (non rollover) */ > >> + if (now >= gd->arch.lastinc) { /* normal (non rollover) */ > >> gd->arch.tbl += (now - gd->arch.lastinc); > >> - else { > >> + } else { > >> /* rollover */ > >> gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) > >> - gd->arch.lastinc) + now; > >> @@ -76,6 +76,7 @@ static ulong get_timer_masked(void) > >> return gd->arch.tbl; > >> } > >> > >> +/* timer without interrupts */ > >> ulong get_timer(ulong base) > >> { > >> return get_timer_masked() - base; > >