From: Aswath Govindraju <a-govindraju@ti.com>
Cc: <u-boot@lists.denx.de>, Sanket Parmar <sparmar@cadence.com>,
Alan Douglas <adouglas@cadence.com>,
Swapnil Jakhade <sjakhade@cadence.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Tero Kristo <kristo@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Aswath Govindraju <a-govindraju@ti.com>
Subject: [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state
Date: Fri, 28 Jan 2022 13:41:28 +0530 [thread overview]
Message-ID: <20220128081152.14901-2-a-govindraju@ti.com> (raw)
In-Reply-To: <20220128081152.14901-1-a-govindraju@ti.com>
From: Sanket Parmar <sparmar@cadence.com>
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <sparmar@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 27 ++++++++++++------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 715def6f173b..6b26b30dcf9d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -606,10 +606,10 @@ static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
- {0x00A5, SIERRA_DET_STANDEC_C_PREG},
+ {0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
- {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
+ {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0xCF00, SIERRA_PSM_DIAG_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
@@ -617,7 +617,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
- {0x0619, SIERRA_PSC_RX_A1_PREG},
+ {0x0003, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
@@ -626,19 +626,19 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
- {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
- {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
- {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
- {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
- {0x8000, SIERRA_CREQ_SPARE_PREG},
+ {0x0000, SIERRA_CREQ_SPARE_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
- {0x8453, SIERRA_CTLELUT_CTRL_PREG},
- {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
- {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
- {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x8452, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
@@ -646,7 +646,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
- {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
@@ -693,6 +693,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
+ {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
--
2.17.1
next prev parent reply other threads:[~2022-01-28 8:12 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
2022-01-28 8:11 ` Aswath Govindraju [this message]
2022-02-08 17:33 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Tom Rini
2022-01-28 8:11 ` [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() " Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0 Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
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