From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A17EEC433F5 for ; Fri, 28 Jan 2022 22:43:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5B11883847; Fri, 28 Jan 2022 23:43:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OqT9XOKa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 92D7383847; Fri, 28 Jan 2022 23:43:17 +0100 (CET) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0C35F8383A for ; Fri, 28 Jan 2022 23:43:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=alpernebiyasak@gmail.com Received: by mail-wr1-x42a.google.com with SMTP id m14so13287628wrg.12 for ; Fri, 28 Jan 2022 14:43:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PQEvif8ErowfuPetczsZdSmm7CSB/B+AUAhEqKZjI20=; b=OqT9XOKaY1rY5ctKHlcF0s1ITo3Ir3rWLopKLaVnOJkoG1/m4H402j3j7xeDywXf18 WxPZwAAVTcokPvAHnhjsx4/iBtogfz0XHtX1cSEei+Mj3adeDAwQ8WEwrJmvQ+T6YYFV QJLaIh0oax/d4DyVEcntlU7Jg6qp0of/h7MK5W70i5CfVzcKoqzEzPLmpGCFAotKQwjI dUGPCsqd63TvHsWlvdd8syBqjdxj7/R5c7tpKXMs/YE3LuFP+MDNMBukhSE43n6mF9G3 ezd/r9rHog1EBOoKogE2zRgpR8EYdOfdKWDHR0sLyVUxMHA28sFTVFfgNz4Ab1wFs62v AHfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQEvif8ErowfuPetczsZdSmm7CSB/B+AUAhEqKZjI20=; b=AsDycwbP7D6rl9TAzxOcjmYYVbYBHi4gyjbmOhjQbRvTJf7RYbhEpqscvtAF270j3x YuQxHSByFElihyx8TwUqfIGDhlFdUs3qL4/1mxNzYv67ANpneZvh4vm65h5KfbNH18FY WtgMiPg+Gb5Yrjcc/h0DU6cu1oZHlYoIjaTi8Aug8JMpyz6VSl/+Mf60bpfMKCQu9tnh fF6X6VRIXrfX+fZudjQySOae3mVPTfhQ6D9rNNf1D6AtheDD7mdlxuoqxd22+hjhxyjs gTVgBHK1lhggqt/EAZKT/Ct6dAzpkvH004AveY9N4vl+jyTynrqJWQNyf/GuX8pVNwz1 /fyg== X-Gm-Message-State: AOAM531HPR/CLLsvnmXwom+x67/yt9RL9YmD5SZjkyYqEQLp0862P7PP PhkIQ7p1Hx8R5Gn05lVvZQGQDgHLLxP3nQ== X-Google-Smtp-Source: ABdhPJxZchLthBTjL7WOjCf+enB8W5juKyD+1qbD0hAs7zx+0MRtpPi8FU1A7ezLfUzRDJAhe/jASw== X-Received: by 2002:a05:6000:1acc:: with SMTP id i12mr454996wry.297.1643409794667; Fri, 28 Jan 2022 14:43:14 -0800 (PST) Received: from localhost.localdomain ([178.233.26.119]) by smtp.gmail.com with ESMTPSA id m8sm5413586wrn.106.2022.01.28.14.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jan 2022 14:43:14 -0800 (PST) From: Alper Nebi Yasak To: u-boot@lists.denx.de Cc: Jack Mitchell , Kever Yang , Heinrich Schuchardt , Yifeng Zhao , Samuel Dionne-Riel , Simon Glass , Aswath Govindraju , Philipp Tomsich , Ashok Reddy Soma , Stephen Carlson , Jaehoon Chung , Michal Simek , Faiz Abbas , Jagan Teki , Peng Fan , Peter Robinson , Alper Nebi Yasak Subject: [PATCH v4 3/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399 Date: Sat, 29 Jan 2022 01:42:38 +0300 Message-Id: <20220128224240.4226-4-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220128224240.4226-1-alpernebiyasak@gmail.com> References: <20220128224240.4226-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On RK3399, a register bit must be set to enable Enhanced Strobe. Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration is requested. However, having it set makes the lower-speed modes stop working and makes reinitialization fail, so let it be unset as needed in set_control_reg(). This is mostly ported from Linux's Arasan SDHCI driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux tree). Signed-off-by: Alper Nebi Yasak --- Changes in v4: - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op Changes in v2: - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue - Don't use unnecessary & for function pointer in ops struct - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES drivers/mmc/rockchip_sdhci.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index b91df05de4ff..f4d5a59036a2 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -42,6 +42,9 @@ ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ PHYCTRL_DLLRDY_DONE) +#define ARASAN_VENDOR_REGISTER 0x78 +#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) + /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) @@ -117,6 +120,19 @@ struct sdhci_data { * Return: 0 if successful, -ve on error */ int (*set_ios_post)(struct sdhci_host *host); + + /** + * set_enhanced_strobe() - Set HS400 Enhanced Strobe config + * + * This is the set_enhanced_strobe() SDHCI operation that should + * be used for the hardware this driver data is associated with. + * Normally, this is used to set any host-specific configuration + * necessary for HS400 ES. + * + * @host: SDHCI host structure + * Return: 0 if successful, -ve on error + */ + int (*set_enhanced_strobe)(struct sdhci_host *host); }; static int rk3399_emmc_phy_init(struct udevice *dev) @@ -206,6 +222,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev) return 0; } +static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + u32 vendor; + + vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER); + if (mmc->selected_mode == MMC_HS_400_ES) + vendor |= ARASAN_VENDOR_ENHANCED_STROBE; + else + vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE; + sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER); + + return 0; +} + static void rk3399_sdhci_set_control_reg(struct sdhci_host *host) { struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); @@ -217,6 +248,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host) rk3399_emmc_phy_power_off(priv->phy); sdhci_set_control_reg(host); + + /* + * Reinitializing the device tries to set it to lower-speed modes + * first, which fails if the Enhanced Strobe bit is set, making + * the device impossible to use. Set the correct value here to + * let reinitialization attempts succeed. + */ + if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) + rk3399_sdhci_set_enhanced_strobe(host); }; static int rk3399_sdhci_set_ios_post(struct sdhci_host *host) @@ -409,10 +449,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) return ret; } +static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); + struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); + + if (data->set_enhanced_strobe) + return data->set_enhanced_strobe(host); + + return -ENOTSUPP; +} + static struct sdhci_ops rockchip_sdhci_ops = { .set_ios_post = rockchip_sdhci_set_ios_post, .platform_execute_tuning = &rockchip_sdhci_execute_tuning, .set_control_reg = rockchip_sdhci_set_control_reg, + .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe, }; static int rockchip_sdhci_probe(struct udevice *dev) @@ -495,6 +547,7 @@ static const struct sdhci_data rk3399_data = { .emmc_phy_init = rk3399_emmc_phy_init, .set_control_reg = rk3399_sdhci_set_control_reg, .set_ios_post = rk3399_sdhci_set_ios_post, + .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe, }; static const struct sdhci_data rk3568_data = { -- 2.34.1