From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15AD2C433F5 for ; Sat, 29 Jan 2022 02:06:04 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C883483282; Sat, 29 Jan 2022 03:06:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id CFD7683575; Sat, 29 Jan 2022 03:05:59 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 339998369F for ; Sat, 29 Jan 2022 03:05:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81BD9D6E; Fri, 28 Jan 2022 18:05:52 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D498F3F7D7; Fri, 28 Jan 2022 18:05:49 -0800 (PST) Date: Sat, 29 Jan 2022 02:05:27 +0000 From: Andre Przywara To: Jesse Taube Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com, hdegoede@redhat.com, sjg@chromium.org, icenowy@aosc.io, marek.behun@nic.cz, festevam@denx.de, narmstrong@baylibre.com, tharvey@gateworks.com, christianshewitt@gmail.com, pbrobinson@gmail.com, jernej.skrabec@gmail.com, hs@denx.de, samuel@sholland.org, arnaud.ferraris@gmail.com, giulio.benetti@benettiengineering.com, thirtythreeforty@gmail.com Subject: Re: [PATCH v2 03/12] arm: arm926ej-s: Add sunxi code Message-ID: <20220129020527.2a36d028@slackpad.fritz.box> In-Reply-To: <20220126135329.2997430-4-Mr.Bossman075@gmail.com> References: <20220126135329.2997430-1-Mr.Bossman075@gmail.com> <20220126135329.2997430-4-Mr.Bossman075@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Wed, 26 Jan 2022 08:53:20 -0500 Jesse Taube wrote: > From: Icenowy Zheng > > Some Allwinner SoCs use ARM926EJ-S core. > > Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory. It looks like we eventually won't need this, since the SPL linker script is basically identical to the v7 one, and the VBAR access in the FEL code could be #ifdef'ed. But I see it's not straight-forward to do this now, so I am OK with this. We can look at cleaning this up later. > Signed-off-by: Icenowy Zheng > Signed-off-by: Jesse Taube Reviewed-by: Andre Przywara Thanks for the changes! Andre > --- > V1->V2: > * Fix Copyright notice > * Remove lowlevel_init > * Remove replaced timer.c > * Remove Read CP15 Control Register > * Remove unused start.c > --- > arch/arm/cpu/arm926ejs/Makefile | 1 + > arch/arm/cpu/arm926ejs/sunxi/Makefile | 5 +++ > arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +++ > arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 33 ++++++++++++++ > arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 48 +++++++++++++++++++++ > 5 files changed, 93 insertions(+) > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds > > diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile > index b901b7c5c9..7f1436d76e 100644 > --- a/arch/arm/cpu/arm926ejs/Makefile > +++ b/arch/arm/cpu/arm926ejs/Makefile > @@ -15,6 +15,7 @@ endif > obj-$(CONFIG_MX27) += mx27/ > obj-$(if $(filter mxs,$(SOC)),y) += mxs/ > obj-$(if $(filter spear,$(SOC)),y) += spear/ > +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ > > # some files can only build in ARM or THUMB2, not THUMB1 > > diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile > new file mode 100644 > index 0000000000..7d8b959dcd > --- /dev/null > +++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# (C) Copyright 2012 Henrik Nordstrom > + > +obj-y += fel_utils.o > +CFLAGS_fel_utils.o := -marm > diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk > new file mode 100644 > index 0000000000..76ffec9df6 > --- /dev/null > +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk > @@ -0,0 +1,6 @@ > +# Build a combined spl + u-boot image > +ifdef CONFIG_SPL > +ifndef CONFIG_SPL_BUILD > +ALL-y += u-boot-sunxi-with-spl.bin > +endif > +endif > diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S > new file mode 100644 > index 0000000000..08be7ed11a > --- /dev/null > +++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Utility functions for FEL mode. > + * > + * Copyright (c) 2015 Google, Inc > + */ > + > +#include > +#include > +#include > +#include > + > +ENTRY(save_boot_params) > + ldr r0, =fel_stash > + str sp, [r0, #0] > + str lr, [r0, #4] > + mrs lr, cpsr @ Read CPSR > + str lr, [r0, #8] > + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register > + str lr, [r0, #12] > + b save_boot_params_ret > +ENDPROC(save_boot_params) > + > +ENTRY(return_to_fel) > + mov sp, r0 > + mov lr, r1 > + ldr r0, =fel_stash > + ldr r1, [r0, #16] > + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register > + ldr r1, [r0, #12] > + msr cpsr, r1 @ Write CPSR > + bx lr > +ENDPROC(return_to_fel) > diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds > new file mode 100644 > index 0000000000..9a000ac5d3 > --- /dev/null > +++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * (C) Copyright 2018 > + * Icenowy Zheng > + * > + * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds: > + */ > +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ > + LENGTH = CONFIG_SPL_MAX_SIZE } > +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ > + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } > + > +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") > +OUTPUT_ARCH(arm) > +ENTRY(_start) > +SECTIONS > +{ > + .text : > + { > + __start = .; > + *(.vectors) > + *(.text*) > + } > .sram > + > + . = ALIGN(4); > + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram > + > + . = ALIGN(4); > + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram > + > + . = ALIGN(4); > + .u_boot_list : { > + KEEP(*(SORT(.u_boot_list*))); > + } > .sram > + > + . = ALIGN(4); > + __image_copy_end = .; > + _end = .; > + > + .bss : > + { > + . = ALIGN(4); > + __bss_start = .; > + *(.bss*) > + . = ALIGN(4); > + __bss_end = .; > + } > .sdram > +}