From: Andre Przywara <andre.przywara@arm.com>
To: Jesse Taube <mr.bossman075@gmail.com>
Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com,
hdegoede@redhat.com, sjg@chromium.org, icenowy@aosc.io,
marek.behun@nic.cz, festevam@denx.de, narmstrong@baylibre.com,
tharvey@gateworks.com, christianshewitt@gmail.com,
pbrobinson@gmail.com, jernej.skrabec@gmail.com, hs@denx.de,
samuel@sholland.org, arnaud.ferraris@gmail.com,
giulio.benetti@benettiengineering.com,
thirtythreeforty@gmail.com
Subject: Re: [PATCH v2 06/12] ARM: sunxi: Add clock and uart to sunxi headers
Date: Sat, 29 Jan 2022 02:11:24 +0000 [thread overview]
Message-ID: <20220129021102.3d879543@slackpad.fritz.box> (raw)
In-Reply-To: <20220126135329.2997430-7-Mr.Bossman075@gmail.com>
On Wed, 26 Jan 2022 08:53:23 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> This patch aims to add header files for the suniv.
> The header files included add support for uart, and clocks.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Thanks for the changes, looks good now.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> V1->V2:
> * Change commit description and topic
> * Change PLL6_CFG_DEFAULT
> * Combine APB1_GATE ifdefs
> * Combine SUNXI_UART0_BASE ifdefs
> * Fix negative logic
> * Remove unused macros
> ---
> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 13 +++++++++++++
> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 ++++++
> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> 4 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
> index cbbe5c7a1e..2cfd540742 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -19,7 +19,7 @@
> #elif defined(CONFIG_SUN50I_GEN_H6)
> #include <asm/arch/clock_sun50i_h6.h>
> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
> - defined(CONFIG_MACH_SUN50I)
> + defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
> #include <asm/arch/clock_sun6i.h>
> #elif defined(CONFIG_MACH_SUN9I)
> #include <asm/arch/clock_sun9i.h>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index ee387127f3..7fcf340db6 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -226,7 +226,12 @@ struct sunxi_ccm_reg {
> #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
> #define CCM_PLL5_CTRL_EN (0x1 << 31)
>
> +#ifdef CONFIG_MACH_SUNIV
> +/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
> +#define PLL6_CFG_DEFAULT 0x90041801
> +#else
> #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
> +#endif
>
> #define CCM_PLL6_CTRL_N_SHIFT 8
> #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
> @@ -488,6 +493,14 @@ struct sunxi_ccm_reg {
> #define AHB_RESET_OFFSET_EPHY 2
> #define AHB_RESET_OFFSET_LVDS 0
>
> +/* apb1 reset */
> +#ifdef CONFIG_MACH_SUNIV
> +#define APB1_GATE_UART_SHIFT (20)
> +#define APB1_GATE_TWI_SHIFT (16)
> +#define APB1_RESET_UART_SHIFT (20)
> +#define APB1_RESET_TWI_SHIFT (16)
> +#endif
> +
> /* apb2 reset */
> #define APB2_RESET_UART_SHIFT (16)
> #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> index d4c795d89c..b7b4564af3 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> @@ -129,9 +129,15 @@ defined(CONFIG_MACH_SUN50I)
> #define SUNXI_CPUCFG_BASE 0x01c25c00
> #endif
>
> +#ifndef CONFIG_MACH_SUNIV
> #define SUNXI_UART0_BASE 0x01c28000
> #define SUNXI_UART1_BASE 0x01c28400
> #define SUNXI_UART2_BASE 0x01c28800
> +#else
> +#define SUNXI_UART0_BASE 0x01c25000
> +#define SUNXI_UART1_BASE 0x01c25400
> +#define SUNXI_UART2_BASE 0x01c25800
> +#endif
> #define SUNXI_UART3_BASE 0x01c28c00
> #define SUNXI_UART4_BASE 0x01c29000
> #define SUNXI_UART5_BASE 0x01c29400
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index f3ab1aea0e..ced69f7dd4 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -165,6 +165,7 @@ enum sunxi_gpio_number {
> #define SUNXI_GPD_LVDS0 3
> #define SUNXI_GPD_PWM 2
>
> +#define SUNIV_GPE_UART0 5
> #define SUN8I_GPE_TWI2 3
> #define SUN50I_GPE_TWI2 3
>
next prev parent reply other threads:[~2022-01-29 2:11 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 13:53 [PATCH v2 00/12] Add support for SUNIV and F1C100s Jesse Taube
2022-01-26 13:53 ` [PATCH v2 01/12] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code Jesse Taube
2022-01-26 13:53 ` [PATCH v2 02/12] mach-sunxi: Move timer code to mach folder Jesse Taube
2022-01-27 10:21 ` Andre Przywara
2022-01-27 20:40 ` Jesse Taube
2022-01-28 0:41 ` Andre Przywara
2022-01-28 4:51 ` Jesse Taube
2022-01-28 14:28 ` Andre Przywara
2022-01-28 22:40 ` Jesse Taube
2022-01-26 13:53 ` [PATCH v2 03/12] arm: arm926ej-s: Add sunxi code Jesse Taube
2022-01-29 2:05 ` Andre Przywara
2022-01-29 2:42 ` Jesse Taube
2022-01-29 11:22 ` Andre Przywara
2022-01-26 13:53 ` [PATCH v2 04/12] dt-bindings: clock: Add initial suniv headers Jesse Taube
2022-01-29 2:05 ` Andre Przywara
2022-01-26 13:53 ` [PATCH v2 05/12] dt-bindings: reset: " Jesse Taube
2022-01-26 13:53 ` [PATCH v2 06/12] ARM: sunxi: Add clock and uart to sunxi headers Jesse Taube
2022-01-29 2:11 ` Andre Przywara [this message]
2022-01-26 13:53 ` [PATCH v2 07/12] sunxi: Add F1C100s DRAM initial support Jesse Taube
2022-01-26 13:53 ` [PATCH v2 08/12] sunxi: board: Add support for SUNIV Jesse Taube
2022-01-26 13:53 ` [PATCH v2 09/12] configs: sunxi: Add common SUNIV header Jesse Taube
2022-01-26 17:43 ` Jesse Taube
2022-01-29 2:18 ` Andre Przywara
2022-01-26 13:53 ` [PATCH v2 10/12] mach-sunxi: Add support for SUNIV architecture Jesse Taube
2022-01-26 13:53 ` [PATCH v2 11/12] ARM: dts: suniv: Add device tree files for F1C100s Jesse Taube
2022-01-29 2:25 ` Andre Przywara
2022-01-29 2:31 ` Jesse Taube
2022-01-29 2:37 ` Andre Przywara
2022-01-29 3:01 ` Jesse Taube
2022-01-29 11:25 ` Andre Przywara
2022-01-26 13:53 ` [PATCH v2 12/12] configs: sunxi: Add support for Lichee Pi Nano Jesse Taube
2022-01-29 2:40 ` [PATCH v2 00/12] Add support for SUNIV and F1C100s Andre Przywara
2022-01-29 2:44 ` Jesse Taube
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220129021102.3d879543@slackpad.fritz.box \
--to=andre.przywara@arm.com \
--cc=arnaud.ferraris@gmail.com \
--cc=christianshewitt@gmail.com \
--cc=festevam@denx.de \
--cc=giulio.benetti@benettiengineering.com \
--cc=hdegoede@redhat.com \
--cc=hs@denx.de \
--cc=icenowy@aosc.io \
--cc=jagan@amarulasolutions.com \
--cc=jernej.skrabec@gmail.com \
--cc=marek.behun@nic.cz \
--cc=mr.bossman075@gmail.com \
--cc=narmstrong@baylibre.com \
--cc=pbrobinson@gmail.com \
--cc=samuel@sholland.org \
--cc=sjg@chromium.org \
--cc=tharvey@gateworks.com \
--cc=thirtythreeforty@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox