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From: Jernej Skrabec <jernej.skrabec@gmail.com>
To: jagan@amarulasolutions.com, andre.przywara@arm.com
Cc: samuel@sholland.org, u-boot@lists.denx.de,
	linux-sunxi@lists.linux.dev,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Subject: [PATCH 2/3] sunxi: clock: H6/H616: Add resistor calibration
Date: Sun, 30 Jan 2022 15:27:14 +0100	[thread overview]
Message-ID: <20220130142715.291427-3-jernej.skrabec@gmail.com> (raw)
In-Reply-To: <20220130142715.291427-1-jernej.skrabec@gmail.com>

BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm/mach-sunxi/clock_sun50i_h6.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index e5846e6381ff..32119ad16555 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -12,9 +12,14 @@ void clock_init_safe(void)
 	struct sunxi_prcm_reg *const prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-	/* this seems to enable PLLs on H616 */
-	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
+	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
+		/* this seems to enable PLLs on H616 */
 		setbits_le32(&prcm->sys_pwroff_gating, 0x10);
+		setbits_le32(&prcm->res_cal_ctrl, 2);
+	}
+
+	clrbits_le32(&prcm->res_cal_ctrl, 1);
+	setbits_le32(&prcm->res_cal_ctrl, 1);
 
 	clock_set_pll1(408000000);
 
-- 
2.35.1


  parent reply	other threads:[~2022-01-30 14:27 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-30 14:27 [PATCH 0/3] sunxi: H6/H616: PRCM updates Jernej Skrabec
2022-01-30 14:27 ` [PATCH 1/3] sunxi: prcm: Add a few registers Jernej Skrabec
2022-01-30 16:29   ` Samuel Holland
2022-01-30 14:27 ` Jernej Skrabec [this message]
2022-01-30 14:27 ` [PATCH 3/3] sunxi: clock: H6: Adjust PLL LDO before clock setup Jernej Skrabec
2022-04-05 22:42 ` [PATCH 0/3] sunxi: H6/H616: PRCM updates Andre Przywara

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