From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A606C433EF for ; Thu, 3 Feb 2022 21:42:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5DD6A838B6; Thu, 3 Feb 2022 22:42:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="moyPy+uv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 70ED583A0F; Thu, 3 Feb 2022 22:42:24 +0100 (CET) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 43A708368F for ; Thu, 3 Feb 2022 22:42:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=nm@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 213LgJhX118434 for ; Thu, 3 Feb 2022 15:42:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643924539; bh=XVBZHtRdbG8Qo8iRIDmvS1to1gH4oa3bjZA/axDebgM=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=moyPy+uv1fT0vwgpKEQL5XWXNfsG5wE3woAfK2Jjp1gf1UZji3/M8Hf/nTWC6j3rS VP3//aXGRxOKkezlZgy2utplW0iD7aO2lPw4z3lvXlZWcN0WMfNX3RFUBmn+itI7Me jZoEbpapFGs/nufIRSfTsvft1x/rkNNImSTOqGr8= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 213LgJEQ006552 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 3 Feb 2022 15:42:19 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 3 Feb 2022 15:42:19 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 3 Feb 2022 15:42:19 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 213LgJ9G051198; Thu, 3 Feb 2022 15:42:19 -0600 Date: Thu, 3 Feb 2022 15:42:19 -0600 From: Nishanth Menon To: Hari Nagalla CC: Subject: Re: [PATCH v1 3/4] arch: arm: mach-k3: am642_init: Probe ESM nodes Message-ID: <20220203214219.gehtg2vg2flf7mp2@grumble> References: <20220202182223.16521-1-hnagalla@ti.com> <20220202182223.16521-4-hnagalla@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20220202182223.16521-4-hnagalla@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 12:22-20220202, Hari Nagalla wrote: One additional comment independent of Christian's comment.. [...] > diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c > index 543dea02bc..cb9495e525 100644 > --- a/arch/arm/mach-k3/am642_init.c > +++ b/arch/arm/mach-k3/am642_init.c > @@ -24,6 +24,8 @@ > #include > > #if defined(CONFIG_SPL_BUILD) > +#define MCU_CTRL_MMR0_BASE 0x04500000 > +#define CTRLMMR_MCU_RST_CTRL 0x04518170 > > static void ctrl_mmr_unlock(void) > { > @@ -42,6 +44,17 @@ static void ctrl_mmr_unlock(void) > mmr_unlock(MCU_PADCFG_MMR1_BASE, 1); > } > > +static void mcu_ctrl_mmr_unlock(void) > +{ There is no real point in spliting this up into mcu_ctrl_mmr_unlock. I'd suggest putting it part of ctrl_mmr_unlock (we already do unlock MCU padconf mmrs there) [...] -- Regards, Nishanth Menon Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D