* [PATCH v1 02/15] rockchip: rk3228-cru: sync the clock dt-binding header from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 03/15] arm: dts: rockchip: sync rk322x.dtsi " Johan Jonker
` (13 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
In order to update the DT for rk3228
sync the clock dt-binding header.
This is the state as of v5.17 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
include/dt-bindings/clock/rk3228-cru.h | 54 +++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 1217d523..de550ea5 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
@@ -39,6 +40,7 @@
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
+#define SCLK_SDIO_SRC 120
#define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122
#define SCLK_HDMI_HDCP 123
@@ -51,6 +53,18 @@
#define SCLK_MAC_TX 130
#define SCLK_MAC_PHY 131
#define SCLK_MAC_OUT 132
+#define SCLK_VDEC_CABAC 133
+#define SCLK_VDEC_CORE 134
+#define SCLK_RGA 135
+#define SCLK_HDCP 136
+#define SCLK_HDMI_CEC 137
+#define SCLK_CRYPTO 138
+#define SCLK_TSP 139
+#define SCLK_HSADC 140
+#define SCLK_WIFI 141
+#define SCLK_OTGPHY0 142
+#define SCLK_OTGPHY1 143
+#define SCLK_HDMI_PHY 144
/* dclk gates */
#define DCLK_VOP 190
@@ -58,15 +72,32 @@
/* aclk gates */
#define ACLK_DMAC 194
+#define ACLK_CPU 195
+#define ACLK_VPU_PRE 196
+#define ACLK_RKVDEC_PRE 197
+#define ACLK_RGA_PRE 198
+#define ACLK_IEP_PRE 199
+#define ACLK_HDCP_PRE 200
+#define ACLK_VOP_PRE 201
+#define ACLK_VPU 202
+#define ACLK_RKVDEC 203
+#define ACLK_IEP 204
+#define ACLK_RGA 205
+#define ACLK_HDCP 206
#define ACLK_PERI 210
#define ACLK_VOP 211
#define ACLK_GMAC 212
+#define ACLK_GPU 213
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
+#define PCLK_VIO_H2P 324
+#define PCLK_HDCP 325
+#define PCLK_EFUSE_1024 326
+#define PCLK_EFUSE_256 327
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
@@ -79,6 +110,7 @@
#define PCLK_TSADC 344
#define PCLK_PWM 350
#define PCLK_TIMER 353
+#define PCLK_CPU 354
#define PCLK_PERI 363
#define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365
@@ -94,6 +126,24 @@
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_CPU 460
+#define HCLK_VPU_PRE 461
+#define HCLK_RKVDEC_PRE 462
+#define HCLK_VIO_PRE 463
+#define HCLK_VPU 464
+#define HCLK_RKVDEC 465
+#define HCLK_VIO 466
+#define HCLK_RGA 467
+#define HCLK_IEP 468
+#define HCLK_VIO_H2P 469
+#define HCLK_HDCP_MMU 470
+#define HCLK_HOST0 471
+#define HCLK_HOST1 472
+#define HCLK_HOST2 473
+#define HCLK_OTG 474
+#define HCLK_TSP 475
+#define HCLK_M_CRYPTO 476
+#define HCLK_S_CRYPTO 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 02/15] rockchip: rk3228-cru: sync the clock dt-binding header from Linux
2022-02-07 3:47 ` [PATCH v1 02/15] rockchip: rk3228-cru: sync the clock " Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> In order to update the DT for rk3228
> sync the clock dt-binding header.
> This is the state as of v5.17 in Linux.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> include/dt-bindings/clock/rk3228-cru.h | 54 +++++++++++++++++++++++++-
> 1 file changed, 52 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 03/15] arm: dts: rockchip: sync rk322x.dtsi from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
2022-02-07 3:47 ` [PATCH v1 02/15] rockchip: rk3228-cru: sync the clock " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 04/15] arm: dts: rockchip: sync rk3229-evb.dts " Johan Jonker
` (12 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
Sync rk322x.dtsi from Linux version 5.17 and add
a rk322x-u-boot.dtsi file for U-boot specific stuff.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk322x-u-boot.dtsi | 54 ++
arch/arm/dts/rk322x.dtsi | 879 +++++++++++++++++++++++++-------
2 files changed, 746 insertions(+), 187 deletions(-)
create mode 100644 arch/arm/dts/rk322x-u-boot.dtsi
diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi
new file mode 100644
index 00000000..ea5e8359
--- /dev/null
+++ b/arch/arm/dts/rk322x-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x9000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x9000>;
+
+ smp-sram@0 {
+ compatible = "rockchip,rk322x-smp-sram";
+ reg = <0x00 0x10>;
+ };
+
+ ddr_sram: ddr-sram@1000 {
+ compatible = "rockchip,rk322x-ddr-sram";
+ reg = <0x1000 0x8000>;
+ };
+ };
+
+ dmc: dmc@11200000 {
+ compatible = "rockchip,rk3228-dmc", "syscon";
+ reg = <0x11200000 0x3fc
+ 0x12000000 0x400>;
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ rockchip,sram = <&ddr_sram>;
+ u-boot,dm-pre-reloc;
+ };
+
+ service_msch: syscon@31090000 {
+ compatible = "rockchip,rk3228-msch", "syscon";
+ reg = <0x31090000 0x2000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ max-frequency = <150000000>;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ max-frequency = <150000000>;
+};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 4a8be5da..8eed9e3a 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -1,7 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -9,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
/ {
#address-cells = <1>;
@@ -20,8 +18,7 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
+ spi0 = &spi0;
};
cpus {
@@ -33,13 +30,11 @@
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHz uV */
- 816000 1000000
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
+ enable-method = "psci";
};
cpu1: cpu@f01 {
@@ -47,6 +42,9 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu2: cpu@f02 {
@@ -54,6 +52,9 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu3: cpu@f03 {
@@ -61,23 +62,37 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ cpu0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
- pdma: pdma@110f0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x110f0000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
};
};
@@ -90,6 +105,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
@@ -107,28 +127,15 @@
#clock-cells = <0>;
};
- bus_intmem@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x9000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x10080000 0x9000>;
- smp-sram@0 {
- compatible = "rockchip,rk322x-smp-sram";
- reg = <0x00 0x10>;
- };
- ddr_sram: ddr-sram@1000 {
- compatible = "rockchip,rk322x-ddr-sram";
- reg = <0x1000 0x8000>;
- };
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
};
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
dmas = <&pdma 14>, <&pdma 15>;
@@ -142,8 +149,6 @@
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
@@ -151,12 +156,23 @@
status = "disabled";
};
+ spdif: spdif@100d0000 {
+ compatible = "rockchip,rk3228-spdif";
+ reg = <0x100d0000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&pdma 10>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ status = "disabled";
+ };
+
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
dmas = <&pdma 0>, <&pdma 1>;
@@ -165,9 +181,124 @@
};
grf: syscon@11000000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3228-grf", "syscon";
+ compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3228-io-voltage-domain";
+ status = "disabled";
+ };
+
+ power: power-controller {
+ compatible = "rockchip,rk3228-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3228_PD_VIO {
+ reg = <RK3228_PD_VIO>;
+ clocks = <&cru ACLK_HDCP>,
+ <&cru SCLK_HDCP>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_iep>,
+ <&qos_rga_r>,
+ <&qos_rga_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VOP {
+ reg = <RK3228_PD_VOP>;
+ clocks =<&cru ACLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_VOP>;
+ pm_qos = <&qos_vop>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VPU {
+ reg = <RK3228_PD_VPU>;
+ clocks = <&cru ACLK_VPU>,
+ <&cru HCLK_VPU>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_RKVDEC {
+ reg = <RK3228_PD_RKVDEC>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ pm_qos = <&qos_rkvdec_r>,
+ <&qos_rkvdec_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_GPU {
+ reg = <RK3228_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ u2phy0: usb2phy@760 {
+ compatible = "rockchip,rk3228-usb2phy";
+ reg = <0x0760 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy0_host: host-port {
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2phy@800 {
+ compatible = "rockchip,rk3228-usb2phy";
+ reg = <0x0800 0x0c>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy1_host: host-port {
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
};
uart0: serial@11010000 {
@@ -206,12 +337,29 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <&uart21_xfer>;
+ pinctrl-0 = <&uart2_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk3228-efuse";
+ reg = <0x11040000 0x20>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x7 0x10>;
+ };
+ cpu_leakage: cpu_leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
@@ -264,12 +412,32 @@
status = "disabled";
};
+ spi0: spi@11090000 {
+ compatible = "rockchip,rk3228-spi";
+ reg = <0x11090000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@110a0000 {
+ compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
+ reg = <0x110a0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_CPU>;
+ status = "disabled";
+ };
+
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
@@ -280,7 +448,6 @@
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
@@ -291,7 +458,6 @@
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
@@ -302,29 +468,48 @@
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};
timer: timer@110c0000 {
- compatible = "rockchip,rk3288-timer";
+ compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
cru: clock-controller@110e0000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
+ assigned-clocks =
+ <&cru PLL_GPLL>, <&cru ARMCLK>,
+ <&cru PLL_CPLL>, <&cru ACLK_PERI>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+ <&cru PCLK_CPU>;
+ assigned-clock-rates =
+ <594000000>, <816000000>,
+ <500000000>, <150000000>,
+ <150000000>, <75000000>,
+ <150000000>, <150000000>,
+ <75000000>;
+ };
+
+ pdma: pdma@110f0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x110f0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
};
thermal-zones {
@@ -356,12 +541,18 @@
map0 {
trip = <&cpu_alert0>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT 6>;
+ <&cpu0 THERMAL_NO_LIMIT 6>,
+ <&cpu1 THERMAL_NO_LIMIT 6>,
+ <&cpu2 THERMAL_NO_LIMIT 6>,
+ <&cpu3 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -373,55 +564,220 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
+ assigned-clocks = <&cru SCLK_TSADC>;
+ assigned-clock-rates = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
- #thermal-sensor-cells = <0>;
+ pinctrl-2 = <&otp_pin>;
+ #thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
- sdmmc: dwmmc@30000000 {
+ hdmi_phy: hdmi-phy@12030000 {
+ compatible = "rockchip,rk3228-hdmi-phy";
+ reg = <0x12030000 0x10000>;
+ clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
+ clock-names = "sysclk", "refoclk", "refpclk";
+ #clock-cells = <0>;
+ clock-output-names = "hdmiphy_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ gpu: gpu@20000000 {
+ compatible = "rockchip,rk3228-mali", "arm,mali-400";
+ reg = <0x20000000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ clock-names = "bus", "core";
+ power-domains = <&power RK3228_PD_GPU>;
+ resets = <&cru SRST_GPU_A>;
+ status = "disabled";
+ };
+
+ vpu: video-codec@20020000 {
+ compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
+ reg = <0x20020000 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3228_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@20020800 {
+ compatible = "rockchip,iommu";
+ reg = <0x20020800 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
+ vdec: video-codec@20030000 {
+ compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
+ reg = <0x20030000 0x480>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <300000000>, <300000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ };
+
+ vdec_mmu: iommu@20030480 {
+ compatible = "rockchip,iommu";
+ reg = <0x20030480 0x40>, <0x200304c0 0x40>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ #iommu-cells = <0>;
+ };
+
+ vop: vop@20050000 {
+ compatible = "rockchip,rk3228-vop";
+ reg = <0x20050000 0x1ffc>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3228_PD_VOP>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@20053f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x20053f00 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VOP>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rga: rga@20060000 {
+ compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
+ reg = <0x20060000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3228_PD_VIO>;
+ resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
+ reset-names = "core", "axi", "ahb";
+ };
+
+ iep_mmu: iommu@20070800 {
+ compatible = "rockchip,iommu";
+ reg = <0x20070800 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmi: hdmi@200a0000 {
+ compatible = "rockchip,rk3228-dw-hdmi";
+ reg = <0x200a0000 0x20000>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru SCLK_HDMI_PHY>;
+ assigned-clock-parents = <&hdmi_phy>;
+ clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "isfr", "iahb", "cec";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
+ resets = <&cru SRST_HDMI_P>;
+ reset-names = "hdmi";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+ };
+ };
+
+ sdmmc: mmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
- max-frequency = <150000000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "disabled";
};
- sdio: dwmmc@30010000 {
+ sdio: mmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
status = "disabled";
};
- emmc: dwmmc@30020000 {
- compatible = "rockchip,rk3288-dw-mshc";
+ emmc: mmc@30020000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
- max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <37500000>;
+ max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
- default-sample-phase = <158>;
- num-slots = <1>;
+ rockchip,default-sample-phase = <158>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
@@ -430,13 +786,79 @@
status = "disabled";
};
- usb20_otg: usb@30040000 {
- compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
+ usb_otg: usb@30040000 {
+ compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- hnp-srp-disable;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb@30080000 {
+ compatible = "generic-ehci";
+ reg = <0x30080000 0x20000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@300a0000 {
+ compatible = "generic-ohci";
+ reg = <0x300a0000 0x20000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@300c0000 {
+ compatible = "generic-ehci";
+ reg = <0x300c0000 0x20000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@300e0000 {
+ compatible = "generic-ohci";
+ reg = <0x300e0000 0x20000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host2_ehci: usb@30100000 {
+ compatible = "generic-ehci";
+ reg = <0x30100000 0x20000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host2_ohci: usb@30120000 {
+ compatible = "generic-ohci";
+ reg = <0x30120000 0x20000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
status = "disabled";
};
@@ -459,6 +881,51 @@
status = "disabled";
};
+ qos_iep: qos@31030080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030080 0x20>;
+ };
+
+ qos_rga_w: qos@31030100 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030100 0x20>;
+ };
+
+ qos_hdcp: qos@31030180 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030180 0x20>;
+ };
+
+ qos_rga_r: qos@31030200 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030200 0x20>;
+ };
+
+ qos_vpu: qos@31040000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31040000 0x20>;
+ };
+
+ qos_gpu: qos@31050000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31050000 0x20>;
+ };
+
+ qos_vop: qos@31060000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31060000 0x20>;
+ };
+
+ qos_rkvdec_r: qos@31070000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070000 0x20>;
+ };
+
+ qos_rkvdec_w: qos@31070080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070080 0x20>;
+ };
+
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -479,7 +946,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@11110000 {
+ gpio0: gpio@11110000 {
compatible = "rockchip,gpio-bank";
reg = <0x11110000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -492,7 +959,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@11120000 {
+ gpio1: gpio@11120000 {
compatible = "rockchip,gpio-bank";
reg = <0x11120000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -505,7 +972,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@11130000 {
+ gpio2: gpio@11130000 {
compatible = "rockchip,gpio-bank";
reg = <0x11130000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -518,7 +985,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@11140000 {
+ gpio3: gpio@11140000 {
compatible = "rockchip,gpio-bank";
reg = <0x11140000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -549,240 +1016,278 @@
sdmmc {
sdmmc_clk: sdmmc-clk {
- rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
};
};
sdio {
sdio_clk: sdio-clk {
- rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
};
sdio_cmd: sdio-cmd {
- rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
};
sdio_bus4: sdio-bus4 {
- rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
};
};
emmc {
emmc_clk: emmc-clk {
- rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ <1 RK_PD3 2 &pcfg_pull_none>,
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ <1 RK_PD5 2 &pcfg_pull_none>,
+ <1 RK_PD6 2 &pcfg_pull_none>,
+ <1 RK_PD7 2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
- rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
+ <2 RK_PB4 1 &pcfg_pull_none>,
+ <2 RK_PD1 1 &pcfg_pull_none>,
+ <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PC5 2 &pcfg_pull_none>,
+ <2 RK_PC4 2 &pcfg_pull_none>,
+ <2 RK_PB3 1 &pcfg_pull_none>,
+ <2 RK_PB0 1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
- rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
- <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
+ <2 RK_PB4 1 &pcfg_pull_none>,
+ <2 RK_PD1 1 &pcfg_pull_none>,
+ <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PB0 1 &pcfg_pull_none>,
+ <2 RK_PB7 1 &pcfg_pull_none>;
};
phy_pins: phy-pins {
- rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
+ <2 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
+ };
+
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
+ <0 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
+ <0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
+ <0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
+ <2 RK_PC5 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+ <0 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_clk: spi0-clk {
+ rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
+ };
+ spi0_cs0: spi0-cs0 {
+ rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ spi0_tx: spi0-tx {
+ rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
+ };
+ spi0_rx: spi0-rx {
+ rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
+ };
+ spi0_cs1: spi0-cs1 {
+ rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
+ };
+ };
+
+ spi1 {
+ spi1_clk: spi1-clk {
+ rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
+ };
+ spi1_cs0: spi1-cs0 {
+ rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
+ };
+ spi1_rx: spi1-rx {
+ rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
+ };
+ spi1_tx: spi1-tx {
+ rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
+ };
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
- rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
+ <0 RK_PB1 1 &pcfg_pull_none>,
+ <0 RK_PB3 1 &pcfg_pull_none>,
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ <0 RK_PB5 1 &pcfg_pull_none>,
+ <0 RK_PB6 1 &pcfg_pull_none>,
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ <1 RK_PA4 2 &pcfg_pull_none>,
+ <1 RK_PA5 2 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
- rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ spdif_tx: spdif-tx {
+ rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
};
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
- rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
- <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
+ <2 RK_PD3 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
- rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
- rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
+ <1 RK_PB2 1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
- rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
- rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
- <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
+ <1 RK_PC3 2 &pcfg_pull_none>;
};
- uart2_cts: uart2-cts {
- rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
+ <1 RK_PB1 2 &pcfg_pull_none>;
};
- uart2_rts: uart2-rts {
- rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ uart2_cts: uart2-cts {
+ rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
};
- };
- uart2-1 {
- uart21_xfer: uart21-xfer {
- rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
- <1 9 RK_FUNC_2 &pcfg_pull_none>;
+ uart2_rts: uart2-rts {
+ rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
};
};
};
-
- dmc: dmc@11200000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3228-dmc", "syscon";
- rockchip,cru = <&cru>;
- rockchip,grf = <&grf>;
- rockchip,msch = <&service_msch>;
- reg = <0x11200000 0x3fc
- 0x12000000 0x400>;
- rockchip,sram = <&ddr_sram>;
- };
-
- service_msch: syscon@31090000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3228-msch", "syscon";
- reg = <0x31090000 0x2000>;
- };
};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 04/15] arm: dts: rockchip: sync rk3229-evb.dts from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
2022-02-07 3:47 ` [PATCH v1 02/15] rockchip: rk3228-cru: sync the clock " Johan Jonker
2022-02-07 3:47 ` [PATCH v1 03/15] arm: dts: rockchip: sync rk322x.dtsi " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 05/15] rockchip: rk3288-power: sync power domain dt-binding header " Johan Jonker
` (11 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
Sync rk3229-evb.dts from Linux version 5.17 and add
a rk3229-evb-u-boot.dtsi file for U-boot specific stuff.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3229-evb-u-boot.dtsi | 28 ++++
arch/arm/dts/rk3229-evb.dts | 223 ++++++++++++++++++++++++----
arch/arm/dts/rk3229.dtsi | 52 +++++++
3 files changed, 274 insertions(+), 29 deletions(-)
create mode 100644 arch/arm/dts/rk3229-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3229.dtsi
diff --git a/arch/arm/dts/rk3229-evb-u-boot.dtsi b/arch/arm/dts/rk3229-evb-u-boot.dtsi
new file mode 100644
index 00000000..b65149c2
--- /dev/null
+++ b/arch/arm/dts/rk3229-evb-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk322x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
+ 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
+ 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
+ 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
+ 0x0 0x924>;
+ rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
+ rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
+ 0 300 3 0 120>;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 632cdc9b..797476e8 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -1,18 +1,16 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
-#include "rk322x.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3229.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- chosen {
- stdout-path = &uart2;
+ aliases {
+ mmc0 = &emmc;
};
memory@60000000 {
@@ -20,6 +18,15 @@
reg = <0x60000000 0x40000000>;
};
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -27,6 +34,18 @@
#clock-cells = <0>;
};
+ vcc_host: vcc-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc_host";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -35,18 +54,95 @@
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&vccio_1v8>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vccio_1v8: vccio-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vccio_3v3: vccio-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power_key: power-key {
+ label = "GPIO Key Power";
+ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <100>;
+ wakeup-source;
+ };
};
};
-&dmc {
- rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
- 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
- 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
- 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
- 0x0 0x924>;
- rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
- rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
- 0 300 3 0 120>;
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ non-removable;
+ status = "okay";
};
&gmac {
@@ -65,27 +161,96 @@
status = "okay";
};
-&emmc {
- u-boot,dm-pre-reloc;
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vccio_3v3>;
+ vccio2-supply = <&vccio_1v8>;
+ vccio4-supply = <&vccio_3v3>;
+};
+
+&pinctrl {
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
status = "okay";
};
-&sdmmc {
+&pwm2 {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
status = "okay";
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- supports-sd;
};
&uart2 {
- u-boot,dm-pre-reloc;
status = "okay";
};
-&usb20_otg {
- status = "okay";
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_ehci {
+ status = "okay";
+};
+
+&usb_host2_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
};
diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi
new file mode 100644
index 00000000..c340fb30
--- /dev/null
+++ b/arch/arm/dts/rk3229.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include "rk322x.dtsi"
+
+/ {
+ compatible = "rockchip,rk3229";
+
+ /delete-node/ opp-table0;
+
+ cpu0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1375000>;
+ };
+ opp-1464000000 {
+ opp-hz = /bits/ 64 <1464000000>;
+ opp-microvolt = <1400000>;
+ };
+ };
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 05/15] rockchip: rk3288-power: sync power domain dt-binding header from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (2 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 04/15] arm: dts: rockchip: sync rk3229-evb.dts " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 06/15] rockchip: rk3288-cru: sync the clock " Johan Jonker
` (10 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
In order to update the DT for rk3288
sync the power domain dt-binding header.
This is the state as of v5.17 in Linux.
Change location to be more in line with other SoCs.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
include/dt-bindings/power-domain/rk3288.h | 11 --------
include/dt-bindings/power/rk3288-power.h | 32 +++++++++++++++++++++++
2 files changed, 32 insertions(+), 11 deletions(-)
delete mode 100644 include/dt-bindings/power-domain/rk3288.h
create mode 100644 include/dt-bindings/power/rk3288-power.h
diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
deleted file mode 100644
index ca68c114..00000000
--- a/include/dt-bindings/power-domain/rk3288.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-
-/* RK3288 power domain index */
-#define RK3288_PD_GPU 0
-#define RK3288_PD_VIO 1
-#define RK3288_PD_VIDEO 2
-#define RK3288_PD_HEVC 3
-#define RK3288_PD_PERI 4
-
-#endif
diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h
new file mode 100644
index 00000000..f710b56c
--- /dev/null
+++ b/include/dt-bindings/power/rk3288-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__
+#define __DT_BINDINGS_POWER_RK3288_POWER_H__
+
+/**
+ * RK3288 Power Domain and Voltage Domain Summary.
+ */
+
+/* VD_CORE */
+#define RK3288_PD_A17_0 0
+#define RK3288_PD_A17_1 1
+#define RK3288_PD_A17_2 2
+#define RK3288_PD_A17_3 3
+#define RK3288_PD_SCU 4
+#define RK3288_PD_DEBUG 5
+#define RK3288_PD_MEM 6
+
+/* VD_LOGIC */
+#define RK3288_PD_BUS 7
+#define RK3288_PD_PERI 8
+#define RK3288_PD_VIO 9
+#define RK3288_PD_ALIVE 10
+#define RK3288_PD_HEVC 11
+#define RK3288_PD_VIDEO 12
+
+/* VD_GPU */
+#define RK3288_PD_GPU 13
+
+/* VD_PMU */
+#define RK3288_PD_PMU 14
+
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 05/15] rockchip: rk3288-power: sync power domain dt-binding header from Linux
2022-02-07 3:47 ` [PATCH v1 05/15] rockchip: rk3288-power: sync power domain dt-binding header " Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> In order to update the DT for rk3288
> sync the power domain dt-binding header.
> This is the state as of v5.17 in Linux.
> Change location to be more in line with other SoCs.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> include/dt-bindings/power-domain/rk3288.h | 11 --------
> include/dt-bindings/power/rk3288-power.h | 32 +++++++++++++++++++++++
> 2 files changed, 32 insertions(+), 11 deletions(-)
> delete mode 100644 include/dt-bindings/power-domain/rk3288.h
> create mode 100644 include/dt-bindings/power/rk3288-power.h
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 06/15] rockchip: rk3288-cru: sync the clock dt-binding header from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (3 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 05/15] rockchip: rk3288-power: sync power domain dt-binding header " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 07/15] arm: dts: rockchip: sync rk3288.dtsi " Johan Jonker
` (9 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
In order to update the DT for rk3288
sync the clock dt-binding header.
This is the state as of v5.17 in Linux.
Keep SCLK_MAC_PLL in use for rk3288 clock driver.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
include/dt-bindings/clock/rk3288-cru.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index e368d767..453f6671 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -1,9 +1,12 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*/
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
@@ -74,6 +77,9 @@
#define SCLK_USBPHY480M_SRC 122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
+#define SCLK_CRYPTO 125
+#define SCLK_MIPIDSI_24M 126
+#define SCLK_VIP_OUT 127
#define SCLK_MAC_PLL 150
#define SCLK_MAC 151
@@ -153,6 +159,9 @@
#define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367
#define PCLK_WDT 368
+#define PCLK_EFUSE256 369
+#define PCLK_EFUSE1024 370
+#define PCLK_ISP_IN 371
/* hclk gates */
#define HCLK_GPS 448
@@ -368,3 +377,5 @@
#define SRST_TSP_CLKIN0 189
#define SRST_TSP_CLKIN1 190
#define SRST_TSP_27M 191
+
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 06/15] rockchip: rk3288-cru: sync the clock dt-binding header from Linux
2022-02-07 3:47 ` [PATCH v1 06/15] rockchip: rk3288-cru: sync the clock " Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> In order to update the DT for rk3288
> sync the clock dt-binding header.
> This is the state as of v5.17 in Linux.
> Keep SCLK_MAC_PLL in use for rk3288 clock driver.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> include/dt-bindings/clock/rk3288-cru.h | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 07/15] arm: dts: rockchip: sync rk3288.dtsi from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (4 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 06/15] rockchip: rk3288-cru: sync the clock " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 08/15] arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files Johan Jonker
` (8 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
Sync rk3288.dtsi from Linux version 5.17 and move
U-boot specific stuff to rk3288-u-boot.dtsi
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-thermal.dtsi | 87 --
arch/arm/dts/rk3288-u-boot.dtsi | 79 +-
arch/arm/dts/rk3288.dtsi | 1521 +++++++++++++++++++-----------
3 files changed, 1036 insertions(+), 651 deletions(-)
delete mode 100644 arch/arm/dts/rk3288-thermal.dtsi
diff --git a/arch/arm/dts/rk3288-thermal.dtsi b/arch/arm/dts/rk3288-thermal.dtsi
deleted file mode 100644
index 87dd8142..00000000
--- a/arch/arm/dts/rk3288-thermal.dtsi
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for RK3288 SoC thermal
- *
- * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-reserve_thermal: reserve_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tsadc 0>;
-
-};
-
-cpu_thermal: cpu_thermal {
- polling-delay-passive = <100>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tsadc 1>;
- linux,hwmon;
-
- trips {
- cpu_alert0: cpu_alert0 {
- temperature = <70000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- cpu_alert1: cpu_alert1 {
- temperature = <75000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- cpu_crit: cpu_crit {
- temperature = <100000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT 6>;
- };
- map1 {
- trip = <&cpu_alert1>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-gpu_thermal: gpu_thermal {
- polling-delay-passive = <100>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tsadc 2>;
- linux,hwmon;
-
- trips {
- gpu_alert0: gpu_alert0 {
- temperature = <80000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- gpu_crit: gpu_crit {
- temperature = <100000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&gpu_alert0>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index e3c6c10f..8a59ec75 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -7,10 +7,52 @@
#include "rockchip-optee.dtsi"
/ {
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ gpio8 = &gpio8;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio0;
+ mmc3 = &sdio1;
+ };
+
chosen {
u-boot,spl-boot-order = \
"same-as-spl", &emmc, &sdmmc;
};
+
+ dmc: dmc@ff610000 {
+ compatible = "rockchip,rk3288-dmc", "syscon";
+ reg = <0x0 0xff610000 0x0 0x3fc
+ 0x0 0xff620000 0x0 0x294
+ 0x0 0xff630000 0x0 0x3fc
+ 0x0 0xff640000 0x0 0x294>;
+ clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
+ <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
+ <&cru ARMCLK>;
+ clock-names = "pclk_ddrupctl0", "pclk_publ0",
+ "pclk_ddrupctl1", "pclk_publ1",
+ "arm_clk";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,noc = <&noc>;
+ rockchip,pmu = <&pmu>;
+ rockchip,sgrf = <&sgrf>;
+ rockchip,sram = <&ddr_sram>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc: syscon@ffac0000 {
+ compatible = "rockchip,rk3288-noc", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x2000>;
+ };
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -37,38 +79,53 @@
};
#endif
-&dmc {
- u-boot,dm-pre-reloc;
+&bus_intmem {
+ ddr_sram: ddr-sram@1000 {
+ compatible = "rockchip,rk3288-ddr-sram";
+ reg = <0x1000 0x4000>;
+ };
};
-&pmu {
+&cru {
u-boot,dm-pre-reloc;
};
-&sgrf {
+&gpio7 {
u-boot,dm-pre-reloc;
};
-&cru {
+&grf {
u-boot,dm-pre-reloc;
};
-&grf {
+&pmu {
u-boot,dm-pre-reloc;
};
-&vopb {
+&sgrf {
u-boot,dm-pre-reloc;
};
-&vopl {
- u-boot,dm-pre-reloc;
+&uart0 {
+ clock-frequency = <24000000>;
+};
+
+&uart1 {
+ clock-frequency = <24000000>;
};
-&noc {
+&uart2 {
+ clock-frequency = <24000000>;
+};
+
+&uart3 {
+ clock-frequency = <24000000>;
+};
+
+&vopb {
u-boot,dm-pre-reloc;
};
-&gpio7 {
+&vopl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 22bb06ce..aaaa6187 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,39 +1,30 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
-#include <dt-bindings/power-domain/rk3288.h>
+#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/video/rk3288.h>
-#include "skeleton.dtsi"
+#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <&gic>;
+
aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- gpio5 = &gpio5;
- gpio6 = &gpio6;
- gpio7 = &gpio7;
- gpio8 = &gpio8;
+ ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- mmc2 = &sdio0;
- mmc3 = &sdio1;
mshc0 = &emmc;
mshc1 = &sdmmc;
mshc2 = &sdio0;
@@ -48,6 +39,15 @@
spi2 = &spi2;
};
+ arm-pmu {
+ compatible = "arm,cortex-a12-pmu";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -58,85 +58,119 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x500>;
- operating-points = <
- /* KHz uV */
- 1800000 1400000
- 1704000 1350000
- 1608000 1300000
- 1512000 1250000
- 1416000 1200000
- 1200000 1100000
- 1008000 1050000
- 816000 1000000
- 696000 950000
- 600000 900000
- 408000 900000
- 216000 900000
- 126000 900000
- >;
+ resets = <&cru SRST_CORE0>;
+ operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
- resets = <&cru SRST_CORE0>;
+ dynamic-power-coefficient = <370>;
};
- cpu@501 {
+ cpu1: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x501>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
- cpu@502 {
+ cpu2: cpu@502 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x502>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
- cpu@503 {
+ cpu3: cpu@503 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x503>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
};
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ cpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
- dmac_peri: dma-controller@ff250000 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xff250000 0x4000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC2>;
- clock-names = "apb_pclk";
- };
-
- dmac_bus_ns: dma-controller@ff600000 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xff600000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- status = "disabled";
+ opp-126000000 {
+ opp-hz = /bits/ 64 <126000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <900000>;
};
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-696000000 {
+ opp-hz = /bits/ 64 <696000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1300000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1350000>;
+ };
+ };
- dmac_bus_s: dma-controller@ffb20000 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xffb20000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The rk3288 cannot use the memory area above 0xfe000000
+ * for dma operations for some reason. While there is
+ * probably a better solution available somewhere, we
+ * haven't found it yet and while devices with 2GB of ram
+ * are not affected, this issue prevents 4GB from booting.
+ * So to make these devices at least bootable, block
+ * this area for the time being until the real solution
+ * is found.
+ */
+ dma-unusable@fe000000 {
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
};
};
@@ -148,14 +182,22 @@
};
timer {
- arm,use-physical-timer;
compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
- always-on;
+ arm,no-tick-in-suspend;
+ };
+
+ timer: timer@ff810000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0x0 0xff810000 0x0 0x20>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
display-subsystem {
@@ -163,61 +205,71 @@
ports = <&vopl_out>, <&vopb_out>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0c0000 0x4000>;
+ reg = <0x0 0xff0c0000 0x0 0x4000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0d0000 0x4000>;
+ reg = <0x0 0xff0d0000 0x0 0x4000>;
+ resets = <&cru SRST_SDIO0>;
+ reset-names = "reset";
status = "disabled";
};
- sdio1: dwmmc@ff0e0000 {
+ sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0e0000 0x4000>;
+ reg = <0x0 0xff0e0000 0x0 0x4000>;
+ resets = <&cru SRST_SDIO1>;
+ reset-names = "reset";
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0f0000 0x4000>;
+ reg = <0x0 0xff0f0000 0x0 0x4000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
saradc: saradc@ff100000 {
compatible = "rockchip,saradc";
- reg = <0xff100000 0x100>;
+ reg = <0x0 0xff100000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
@@ -230,7 +282,7 @@
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
- reg = <0xff110000 0x1000>;
+ reg = <0x0 0xff110000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -245,7 +297,7 @@
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
- reg = <0xff120000 0x1000>;
+ reg = <0x0 0xff120000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -260,7 +312,7 @@
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
- reg = <0xff130000 0x1000>;
+ reg = <0x0 0xff130000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -268,7 +320,7 @@
i2c1: i2c@ff140000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff140000 0x1000>;
+ reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -281,7 +333,7 @@
i2c3: i2c@ff150000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff150000 0x1000>;
+ reg = <0x0 0xff150000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -294,7 +346,7 @@
i2c4: i2c@ff160000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff160000 0x1000>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -307,7 +359,7 @@
i2c5: i2c@ff170000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff170000 0x1000>;
+ reg = <0x0 0xff170000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -317,15 +369,17 @@
pinctrl-0 = <&i2c5_xfer>;
status = "disabled";
};
+
uart0: serial@ff180000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff180000 0x100>;
+ reg = <0x0 0xff180000 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
@@ -333,13 +387,14 @@
uart1: serial@ff190000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff190000 0x100>;
+ reg = <0x0 0xff190000 0x0 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 3>, <&dmac_peri 4>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -347,26 +402,27 @@
uart2: serial@ff690000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff690000 0x100>;
+ reg = <0x0 0xff690000 0x0 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "disabled";
};
+
uart3: serial@ff1b0000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff1b0000 0x100>;
+ reg = <0x0 0xff1b0000 0x0 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 7>, <&dmac_peri 8>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
status = "disabled";
@@ -374,41 +430,136 @@
uart4: serial@ff1c0000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff1c0000 0x100>;
+ reg = <0x0 0xff1c0000 0x0 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 9>, <&dmac_peri 10>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
- thermal: thermal-zones {
- #include "rk3288-thermal.dtsi"
+
+ dmac_peri: dma-controller@ff250000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff250000 0x0 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+
+ thermal-zones {
+ reserve_thermal: reserve-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ };
+
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT 6>,
+ <&cpu1 THERMAL_NO_LIMIT 6>,
+ <&cpu2 THERMAL_NO_LIMIT 6>,
+ <&cpu3 THERMAL_NO_LIMIT 6>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 2>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
tsadc: tsadc@ff280000 {
compatible = "rockchip,rk3288-tsadc";
- reg = <0xff280000 0x100>;
+ reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "otp_out";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_pin>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
- hw-shut-temp = <125000>;
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
gmac: ethernet@ff290000 {
compatible = "rockchip,rk3288-gmac";
- reg = <0xff290000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ reg = <0x0 0xff290000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_MAC>,
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
@@ -418,20 +569,22 @@
"mac_clk_rx", "mac_clk_tx",
"clk_mac_ref", "clk_mac_refout",
"aclk_mac", "pclk_mac";
+ resets = <&cru SRST_MAC>;
+ reset-names = "stmmaceth";
+ status = "disabled";
};
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0xff500000 0x100>;
+ reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>;
- clock-names = "usbhost";
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
};
- /* NOTE: doesn't work on RK3288, but fixed on RK3288W */
+ /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
usb_host0_ohci: usb@ff520000 {
compatible = "generic-ohci";
reg = <0x0 0xff520000 0x0 0x100>;
@@ -445,23 +598,28 @@
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
- reg = <0xff540000 0x40000>;
+ reg = <0x0 0xff540000 0x0 0x40000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST1>;
clock-names = "otg";
+ dr_mode = "host";
phys = <&usbphy2>;
phy-names = "usb2-phy";
+ snps,reset-phy-on-wake;
status = "disabled";
};
usb_otg: usb@ff580000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
- reg = <0xff580000 0x40000>;
+ reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG0>;
clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -469,36 +627,28 @@
usb_hsic: usb@ff5c0000 {
compatible = "generic-ehci";
- reg = <0xff5c0000 0x100>;
+ reg = <0x0 0xff5c0000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HSIC>;
- clock-names = "usbhost";
status = "disabled";
};
- dmc: dmc@ff610000 {
- compatible = "rockchip,rk3288-dmc", "syscon";
- rockchip,cru = <&cru>;
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmu>;
- rockchip,sgrf = <&sgrf>;
- rockchip,noc = <&noc>;
- reg = <0xff610000 0x3fc
- 0xff620000 0x294
- 0xff630000 0x3fc
- 0xff640000 0x294>;
- rockchip,sram = <&ddr_sram>;
- clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
- <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
- <&cru ARMCLK>;
- clock-names = "pclk_ddrupctl0", "pclk_publ0",
- "pclk_ddrupctl1", "pclk_publ1",
- "arm_clk";
+ dmac_bus_ns: dma-controller@ff600000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff600000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ status = "disabled";
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff650000 0x1000>;
+ reg = <0x0 0xff650000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -511,7 +661,7 @@
i2c2: i2c@ff660000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff660000 0x1000>;
+ reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -524,86 +674,194 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680000 0x10>;
+ reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680010 0x10>;
+ reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680020 0x10>;
+ reg = <0x0 0xff680020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680030 0x10>;
- #pwm-cells = <2>;
+ reg = <0x0 0xff680030 0x0 0x10>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
- bus_intmem@ff700000 {
+ bus_intmem: sram@ff700000 {
compatible = "mmio-sram";
- reg = <0xff700000 0x18000>;
+ reg = <0x0 0xff700000 0x0 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0xff700000 0x18000>;
+ ranges = <0 0x0 0xff700000 0x18000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
- ddr_sram: ddr-sram@1000 {
- compatible = "rockchip,rk3288-ddr-sram";
- reg = <0x1000 0x4000>;
- };
};
- sram@ff720000 {
+ pmu_sram: sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
- reg = <0xff720000 0x1000>;
+ reg = <0x0 0xff720000 0x0 0x1000>;
};
pmu: power-management@ff730000 {
- compatible = "rockchip,rk3288-pmu", "syscon";
- reg = <0xff730000 0x100>;
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff730000 0x0 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&cru SCLK_EDP_24M>;
+ assigned-clock-parents = <&xin24m>;
+
+ /*
+ * Note: Although SCLK_* are the working clocks
+ * of device without including on the NOC, needed for
+ * synchronous reset.
+ *
+ * The clocks on the which NOC:
+ * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+ * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+ * ACLK_RGA is on ACLK_RGA_NIU.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ *
+ * Which clock are device clocks:
+ * clocks devices
+ * *_IEP IEP:Image Enhancement Processor
+ * *_ISP ISP:Image Signal Processing
+ * *_VIP VIP:Video Input Processor
+ * *_VOP* VOP:Visual Output Processor
+ * *_RGA RGA
+ * *_EDP* EDP
+ * *_LVDS_* LVDS
+ * *_HDMI HDMI
+ * *_MIPI_* MIPI
+ */
+ power-domain@RK3288_PD_VIO {
+ reg = <RK3288_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_VOP0>,
+ <&cru ACLK_VOP1>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_LVDS_PHY>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_ISP_JPE>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_vio0_iep>,
+ <&qos_vio1_vop>,
+ <&qos_vio1_isp_w0>,
+ <&qos_vio1_isp_w1>,
+ <&qos_vio0_vop>,
+ <&qos_vio0_vip>,
+ <&qos_vio2_rga_r>,
+ <&qos_vio2_rga_w>,
+ <&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: The following 3 are HEVC(H.265) clocks,
+ * and on the ACLK_HEVC_NIU (NOC).
+ */
+ power-domain@RK3288_PD_HEVC {
+ reg = <RK3288_PD_HEVC>;
+ clocks = <&cru ACLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_hevc_r>,
+ <&qos_hevc_w>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+ * (video endecoder & decoder) clocks that on the
+ * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ */
+ power-domain@RK3288_PD_VIDEO {
+ reg = <RK3288_PD_VIDEO>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: ACLK_GPU is the GPU clock,
+ * and on the ACLK_GPU_NIU (NOC).
+ */
+ power-domain@RK3288_PD_GPU {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu_r>,
+ <&qos_gpu_w>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x94>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
};
sgrf: syscon@ff740000 {
compatible = "rockchip,rk3288-sgrf", "syscon";
- reg = <0xff740000 0x1000>;
+ reg = <0x0 0xff740000 0x0 0x1000>;
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3288-cru";
- reg = <0xff760000 0x1000>;
+ reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -620,27 +878,77 @@
};
grf: syscon@ff770000 {
- compatible = "rockchip,rk3288-grf", "syscon";
- reg = <0xff770000 0x1000>;
+ compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff770000 0x0 0x1000>;
+
+ edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3288-io-voltage-domain";
+ status = "disabled";
+ };
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@320 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBOTG_PHY>;
+ reset-names = "phy-reset";
+ };
+
+ usbphy1: usb-phy@334 {
+ #phy-cells = <0>;
+ reg = <0x334>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBHOST0_PHY>;
+ reset-names = "phy-reset";
+ };
+
+ usbphy2: usb-phy@348 {
+ #phy-cells = <0>;
+ reg = <0x348>;
+ clocks = <&cru SCLK_OTGPHY2>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBHOST1_PHY>;
+ reset-names = "phy-reset";
+ };
+ };
};
wdt: watchdog@ff800000 {
compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
- reg = <0xff800000 0x100>;
+ reg = <0x0 0xff800000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spdif: sound@ff88b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
- reg = <0xff8b0000 0x10000>;
+ reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
- clock-names = "hclk", "mclk";
- clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
+ clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
+ clock-names = "mclk", "hclk";
dmas = <&dmac_bus_s 3>;
dma-names = "tx";
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
rockchip,grf = <&grf>;
@@ -649,59 +957,108 @@
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
- reg = <0xff890000 0x10000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <1>;
+ reg = <0x0 0xff890000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <2>;
+ status = "disabled";
+ };
+
+ crypto: cypto-controller@ff8a0000 {
+ compatible = "rockchip,rk3288-crypto";
+ reg = <0x0 0xff8a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
+ <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ status = "okay";
+ };
+
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x40>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
status = "disabled";
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rk3288-rga";
+ reg = <0x0 0xff920000 0x0 0x180>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3288_PD_VIO>;
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+ reset-names = "core", "axi", "ahb";
+ };
+
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff930000 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
- power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
+
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
- vopb_out_edp: endpoint@0 {
+
+ vopb_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&edp_in_vopb>;
+ remote-endpoint = <&hdmi_in_vopb>;
};
- vopb_out_hdmi: endpoint@1 {
+
+ vopb_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <&hdmi_in_vopb>;
+ remote-endpoint = <&edp_in_vopb>;
};
- vopb_out_lvds: endpoint@2 {
+
+ vopb_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <&lvds_in_vopb>;
- };
- vopb_out_mipi: endpoint@3 {
- reg = <3>;
remote-endpoint = <&mipi_in_vopb>;
};
+ vopb_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopb>;
+ };
};
};
vopb_mmu: iommu@ff930300 {
compatible = "rockchip,iommu";
- reg = <0xff930300 0x100>;
+ reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
@@ -709,277 +1066,365 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff940000 0x19c>;
+ reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
- power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
+
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_edp: endpoint@0 {
+
+ vopl_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&edp_in_vopl>;
+ remote-endpoint = <&hdmi_in_vopl>;
};
- vopl_out_hdmi: endpoint@1 {
+
+ vopl_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <&hdmi_in_vopl>;
+ remote-endpoint = <&edp_in_vopl>;
};
- vopl_out_lvds: endpoint@2 {
+
+ vopl_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <&lvds_in_vopl>;
- };
- vopl_out_mipi: endpoint@3 {
- reg = <3>;
remote-endpoint = <&mipi_in_vopl>;
};
+ vopl_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopl>;
+ };
};
};
vopl_mmu: iommu@ff940300 {
compatible = "rockchip,iommu";
- reg = <0xff940300 0x100>;
+ reg = <0x0 0xff940300 0x0 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
- edp: edp@ff970000 {
- compatible = "rockchip,rk3288-edp";
- reg = <0xff970000 0x4000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
- rockchip,grf = <&grf>;
- clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
- resets = <&cru 111>;
- reset-names = "edp";
+ mipi_dsi: mipi@ff960000 {
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
power-domains = <&power RK3288_PD_VIO>;
+ rockchip,grf = <&grf>;
status = "disabled";
+
ports {
- edp_in: port {
+ mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
- edp_in_vopb: endpoint@0 {
+ mipi_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_edp>;
+ remote-endpoint = <&vopb_out_mipi>;
};
- edp_in_vopl: endpoint@1 {
+ mipi_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_edp>;
+ remote-endpoint = <&vopl_out_mipi>;
};
};
};
};
- hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff980000 0x20000>;
- reg-io-width = <4>;
- ddc-i2c-bus = <&i2c5>;
+ lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ reg = <0x0 0xff96c000 0x0 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
status = "disabled";
+
ports {
- hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in: port@0 {
+ reg = <0>;
+
#address-cells = <1>;
#size-cells = <0>;
- hdmi_in_vopb: endpoint@0 {
+
+ lvds_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_hdmi>;
+ remote-endpoint = <&vopb_out_lvds>;
};
- hdmi_in_vopl: endpoint@1 {
+ lvds_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
+ remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
- lvds: lvds@ff96c000 {
- compatible = "rockchip,rk3288-lvds";
- reg = <0xff96c000 0x4000>;
- clocks = <&cru PCLK_LVDS_PHY>;
- clock-names = "pclk_lvds";
- pinctrl-names = "default";
- pinctrl-0 = <&lcdc0_ctl>;
+ edp: dp@ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0x0 0xff970000 0x0 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&edp_phy>;
+ phy-names = "dp";
+ resets = <&cru SRST_EDP>;
+ reset-names = "dp";
rockchip,grf = <&grf>;
status = "disabled";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
- lvds_in: port@0 {
+ edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
- lvds_in_vopb: endpoint@0 {
+ edp_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_lvds>;
+ remote-endpoint = <&vopb_out_edp>;
};
- lvds_in_vopl: endpoint@1 {
+ edp_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_lvds>;
+ remote-endpoint = <&vopl_out_edp>;
};
};
};
};
- mipi_dsi0: mipi@ff960000 {
- compatible = "rockchip,rk3288_mipi_dsi";
- reg = <0xff960000 0x4000>;
- clocks = <&cru PCLK_MIPI_DSI0>;
- clock-names = "pclk_mipi";
- /*pinctrl-names = "default";
- pinctrl-0 = <&lcdc0_ctl>;*/
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3288-dw-hdmi";
+ reg = <0x0 0xff980000 0x0 0x20000>;
+ reg-io-width = <4>;
+ #sound-dai-cells = <0>;
rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "iahb", "isfr", "cec";
+ power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
+
ports {
- reg = <1>;
- mipi_in: port {
+ hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
- mipi_in_vopb: endpoint@0 {
+ hdmi_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_mipi>;
+ remote-endpoint = <&vopb_out_hdmi>;
};
- mipi_in_vopl: endpoint@1 {
+ hdmi_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_mipi>;
+ remote-endpoint = <&vopl_out_hdmi>;
};
};
};
};
- hdmi_audio: hdmi_audio {
- compatible = "rockchip,rk3288-hdmi-audio";
- i2s-controller = <&i2s>;
- status = "disable";
- };
-
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
- reg = <0xff9a0000 0x800>;
+ reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- power-domains = <&power RK3288_PD_VIDEO>;
+ clock-names = "aclk", "hclk";
iommus = <&vpu_mmu>;
+ power-domains = <&power RK3288_PD_VIDEO>;
};
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
- reg = <0xff9a0800 0x100>;
+ reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
power-domains = <&power RK3288_PD_VIDEO>;
+ };
+
+ hevc_mmu: iommu@ff9c0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ status = "disabled";
};
gpu: gpu@ffa30000 {
- compatible = "arm,malit764",
- "arm,malit76x",
- "arm,malit7xx",
- "arm,mali-midgard";
- reg = <0xffa30000 0x10000>;
+ compatible = "rockchip,rk3288-mali", "arm,mali-t760";
+ reg = <0x0 0xffa30000 0x0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "JOB", "MMU", "GPU";
+ interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
- clock-names = "aclk_gpu";
- operating-points = <
- /* KHz uV */
- 100000 950000
- 200000 950000
- 300000 1000000
- 400000 1100000
- /* 500000 1200000 - See crosbug.com/p/33857 */
- 600000 1250000
- >;
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
power-domains = <&power RK3288_PD_GPU>;
status = "disabled";
};
- noc: syscon@ffac0000 {
- compatible = "rockchip,rk3288-noc", "syscon";
- reg = <0xffac0000 0x2000>;
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1250000>;
+ };
};
- efuse: efuse@ffb40000 {
- compatible = "rockchip,rk3288-efuse";
- reg = <0xffb40000 0x10000>;
- status = "disabled";
+ qos_gpu_r: qos@ffaa0000 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffaa0000 0x0 0x20>;
};
- gic: interrupt-controller@ffc01000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
+ qos_gpu_w: qos@ffaa0080 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffaa0080 0x0 0x20>;
+ };
- reg = <0xffc01000 0x1000>,
- <0xffc02000 0x1000>,
- <0xffc04000 0x2000>,
- <0xffc06000 0x2000>;
- interrupts = <GIC_PPI 9 0xf04>;
+ qos_vio1_vop: qos@ffad0000 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0000 0x0 0x20>;
};
- cpuidle: cpuidle {
- compatible = "rockchip,rk3288-cpuidle";
+ qos_vio1_isp_w0: qos@ffad0100 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0100 0x0 0x20>;
};
- usbphy: phy {
- compatible = "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
+ qos_vio1_isp_w1: qos@ffad0180 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0180 0x0 0x20>;
+ };
+
+ qos_vio0_vop: qos@ffad0400 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0400 0x0 0x20>;
+ };
+
+ qos_vio0_vip: qos@ffad0480 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0480 0x0 0x20>;
+ };
+
+ qos_vio0_iep: qos@ffad0500 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0500 0x0 0x20>;
+ };
+
+ qos_vio2_rga_r: qos@ffad0800 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0800 0x0 0x20>;
+ };
+
+ qos_vio2_rga_w: qos@ffad0880 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0880 0x0 0x20>;
+ };
+
+ qos_vio1_isp_r: qos@ffad0900 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffad0900 0x0 0x20>;
+ };
+
+ qos_video: qos@ffae0000 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffae0000 0x0 0x20>;
+ };
+
+ qos_hevc_r: qos@ffaf0000 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffaf0000 0x0 0x20>;
+ };
+
+ qos_hevc_w: qos@ffaf0080 {
+ compatible = "rockchip,rk3288-qos", "syscon";
+ reg = <0x0 0xffaf0080 0x0 0x20>;
+ };
+
+ dmac_bus_s: dma-controller@ffb20000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xffb20000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ };
+
+ efuse: efuse@ffb40000 {
+ compatible = "rockchip,rk3288-efuse";
+ reg = <0x0 0xffb40000 0x0 0x20>;
#address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
- usbphy0: usb-phy0 {
- #phy-cells = <0>;
- reg = <0x320>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
+ cpu_id: cpu-id@7 {
+ reg = <0x07 0x10>;
};
-
- usbphy1: usb-phy1 {
- #phy-cells = <0>;
- reg = <0x334>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
+ cpu_leakage: cpu_leakage@17 {
+ reg = <0x17 0x1>;
};
+ };
- usbphy2: usb-phy2 {
- #phy-cells = <0>;
- reg = <0x348>;
- clocks = <&cru SCLK_OTGPHY2>;
- clock-names = "phyclk";
- };
+ gic: interrupt-controller@ffc01000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x0 0xffc01000 0x0 0x1000>,
+ <0x0 0xffc02000 0x0 0x2000>,
+ <0x0 0xffc04000 0x0 0x2000>,
+ <0x0 0xffc06000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
- gpio0: gpio0@ff750000 {
+ gpio0: gpio@ff750000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff750000 0x100>;
+ reg = <0x0 0xff750000 0x0 0x100>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
@@ -990,9 +1435,9 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff780000 {
+ gpio1: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff780000 0x100>;
+ reg = <0x0 0xff780000 0x0 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
@@ -1003,9 +1448,9 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff790000 {
+ gpio2: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff790000 0x100>;
+ reg = <0x0 0xff790000 0x0 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
@@ -1016,9 +1461,9 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff7a0000 {
+ gpio3: gpio@ff7a0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7a0000 0x100>;
+ reg = <0x0 0xff7a0000 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
@@ -1029,9 +1474,9 @@
#interrupt-cells = <2>;
};
- gpio4: gpio4@ff7b0000 {
+ gpio4: gpio@ff7b0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7b0000 0x100>;
+ reg = <0x0 0xff7b0000 0x0 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
@@ -1042,9 +1487,9 @@
#interrupt-cells = <2>;
};
- gpio5: gpio5@ff7c0000 {
+ gpio5: gpio@ff7c0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7c0000 0x100>;
+ reg = <0x0 0xff7c0000 0x0 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO5>;
@@ -1055,9 +1500,9 @@
#interrupt-cells = <2>;
};
- gpio6: gpio6@ff7d0000 {
+ gpio6: gpio@ff7d0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7d0000 0x100>;
+ reg = <0x0 0xff7d0000 0x0 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO6>;
@@ -1068,9 +1513,9 @@
#interrupt-cells = <2>;
};
- gpio7: gpio7@ff7e0000 {
+ gpio7: gpio@ff7e0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7e0000 0x100>;
+ reg = <0x0 0xff7e0000 0x0 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO7>;
@@ -1081,9 +1526,9 @@
#interrupt-cells = <2>;
};
- gpio8: gpio8@ff7f0000 {
+ gpio8: gpio@ff7f0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7f0000 0x100>;
+ reg = <0x0 0xff7f0000 0x0 0x100>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO8>;
@@ -1098,6 +1543,24 @@
hdmi_cec_c0: hdmi-cec-c0 {
rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
};
+
+ hdmi_cec_c7: hdmi-cec-c7 {
+ rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ hdmi_ddc: hdmi-ddc {
+ rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
+ <7 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ hdmi_ddc_unwedge: hdmi-ddc-unwedge {
+ rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
+ <7 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
};
pcfg_pull_up: pcfg-pull-up {
@@ -1117,472 +1580,424 @@
drive-strength = <12>;
};
- sleep {
+ suspend {
global_pwroff: global-pwroff {
- rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
- rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
};
ddr0_retention: ddr0-retention {
- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
};
ddr1_retention: ddr1-retention {
- rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
+ };
+ };
+
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
- <0 16 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
+ <0 RK_PC0 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
- <8 5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
+ <8 RK_PA5 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
- <6 10 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
+ <6 RK_PB2 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
- <2 17 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PC1 1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
- rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
- <7 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
+ <7 RK_PC2 1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
- rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
- <7 20 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
+ <7 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
- rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
- <6 1 RK_FUNC_1 &pcfg_pull_none>,
- <6 2 RK_FUNC_1 &pcfg_pull_none>,
- <6 3 RK_FUNC_1 &pcfg_pull_none>,
- <6 4 RK_FUNC_1 &pcfg_pull_none>,
- <6 8 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
+ <6 RK_PA1 1 &pcfg_pull_none>,
+ <6 RK_PA2 1 &pcfg_pull_none>,
+ <6 RK_PA3 1 &pcfg_pull_none>,
+ <6 RK_PA4 1 &pcfg_pull_none>,
+ <6 RK_PB0 1 &pcfg_pull_none>;
};
};
- lcdc0 {
- lcdc0_ctl: lcdc0-ctl {
- rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
- <1 25 RK_FUNC_1 &pcfg_pull_none>,
- <1 26 RK_FUNC_1 &pcfg_pull_none>,
- <1 27 RK_FUNC_1 &pcfg_pull_none>;
+ lcdc {
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ <1 RK_PD3 1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
};
- sdmmc_cd: sdmcc-cd {
- rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+ sdmmc_cd: sdmmc-cd {
+ rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
- <6 17 RK_FUNC_1 &pcfg_pull_up>,
- <6 18 RK_FUNC_1 &pcfg_pull_up>,
- <6 19 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
+ <6 RK_PC1 1 &pcfg_pull_up>,
+ <6 RK_PC2 1 &pcfg_pull_up>,
+ <6 RK_PC3 1 &pcfg_pull_up>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
- <4 21 RK_FUNC_1 &pcfg_pull_up>,
- <4 22 RK_FUNC_1 &pcfg_pull_up>,
- <4 23 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
+ <4 RK_PC5 1 &pcfg_pull_up>,
+ <4 RK_PC6 1 &pcfg_pull_up>,
+ <4 RK_PC7 1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
- rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
- rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
- rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
- rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
- rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
- rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
- rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
};
};
sdio1 {
sdio1_bus1: sdio1-bus1 {
- rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
};
sdio1_bus4: sdio1-bus4 {
- rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
- <3 25 RK_FUNC_4 &pcfg_pull_up>,
- <3 26 RK_FUNC_4 &pcfg_pull_up>,
- <3 27 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
+ <3 RK_PD1 4 &pcfg_pull_up>,
+ <3 RK_PD2 4 &pcfg_pull_up>,
+ <3 RK_PD3 4 &pcfg_pull_up>;
};
sdio1_cd: sdio1-cd {
- rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
};
sdio1_wp: sdio1-wp {
- rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
};
sdio1_bkpwr: sdio1-bkpwr {
- rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
};
sdio1_int: sdio1-int {
- rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
};
sdio1_cmd: sdio1-cmd {
- rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
};
sdio1_clk: sdio1-clk {
- rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
};
sdio1_pwr: sdio1-pwr {
- rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
};
};
emmc {
emmc_clk: emmc-clk {
- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
- rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
- <3 1 RK_FUNC_2 &pcfg_pull_up>,
- <3 2 RK_FUNC_2 &pcfg_pull_up>,
- <3 3 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+ <3 RK_PA1 2 &pcfg_pull_up>,
+ <3 RK_PA2 2 &pcfg_pull_up>,
+ <3 RK_PA3 2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
- <3 1 RK_FUNC_2 &pcfg_pull_up>,
- <3 2 RK_FUNC_2 &pcfg_pull_up>,
- <3 3 RK_FUNC_2 &pcfg_pull_up>,
- <3 4 RK_FUNC_2 &pcfg_pull_up>,
- <3 5 RK_FUNC_2 &pcfg_pull_up>,
- <3 6 RK_FUNC_2 &pcfg_pull_up>,
- <3 7 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
+ <3 RK_PA1 2 &pcfg_pull_up>,
+ <3 RK_PA2 2 &pcfg_pull_up>,
+ <3 RK_PA3 2 &pcfg_pull_up>,
+ <3 RK_PA4 2 &pcfg_pull_up>,
+ <3 RK_PA5 2 &pcfg_pull_up>,
+ <3 RK_PA6 2 &pcfg_pull_up>,
+ <3 RK_PA7 2 &pcfg_pull_up>;
};
};
spi0 {
spi0_clk: spi0-clk {
- rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
- rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
- rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
- rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
- rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
- rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
- rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
- rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
- rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
};
};
spi2 {
spi2_cs1: spi2-cs1 {
- rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
};
spi2_clk: spi2-clk {
- rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
- rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
- rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
- rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
- <4 17 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
+ <4 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
- rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
};
uart0_rts: uart0-rts {
- rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
- <5 9 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
+ <5 RK_PB1 1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
- rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
};
uart1_rts: uart1-rts {
- rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
- <7 23 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
+ <7 RK_PC7 1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
- rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
- <7 8 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
+ <7 RK_PB0 1 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
- rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
};
uart3_rts: uart3-rts {
- rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
- rockchip,pins = <5 12 3 &pcfg_pull_up>,
- <5 13 3 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
+ <5 RK_PB6 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
- rockchip,pins = <5 14 3 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
};
uart4_rts: uart4-rts {
- rockchip,pins = <5 15 3 &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
};
};
tsadc {
+ otp_pin: otp-pin {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
otp_out: otp-out {
- rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
- rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
- rockchip,pins = <3 30 3 &pcfg_pull_none>,
- <3 31 3 &pcfg_pull_none>,
- <3 26 3 &pcfg_pull_none>,
- <3 27 3 &pcfg_pull_none>,
- <3 28 3 &pcfg_pull_none_12ma>,
- <3 29 3 &pcfg_pull_none_12ma>,
- <3 24 3 &pcfg_pull_none_12ma>,
- <3 25 3 &pcfg_pull_none_12ma>,
- <4 0 3 &pcfg_pull_none>,
- <4 5 3 &pcfg_pull_none>,
- <4 6 3 &pcfg_pull_none>,
- <4 9 3 &pcfg_pull_none_12ma>,
- <4 4 3 &pcfg_pull_none_12ma>,
- <4 1 3 &pcfg_pull_none>,
- <4 3 3 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD2 3 &pcfg_pull_none>,
+ <3 RK_PD3 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none_12ma>,
+ <3 RK_PD5 3 &pcfg_pull_none_12ma>,
+ <3 RK_PD0 3 &pcfg_pull_none_12ma>,
+ <3 RK_PD1 3 &pcfg_pull_none_12ma>,
+ <4 RK_PA0 3 &pcfg_pull_none>,
+ <4 RK_PA5 3 &pcfg_pull_none>,
+ <4 RK_PA6 3 &pcfg_pull_none>,
+ <4 RK_PB1 3 &pcfg_pull_none_12ma>,
+ <4 RK_PA4 3 &pcfg_pull_none_12ma>,
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ <4 RK_PA3 3 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
- rockchip,pins = <3 30 3 &pcfg_pull_none>,
- <3 31 3 &pcfg_pull_none>,
- <3 28 3 &pcfg_pull_none>,
- <3 29 3 &pcfg_pull_none>,
- <4 0 3 &pcfg_pull_none>,
- <4 5 3 &pcfg_pull_none>,
- <4 4 3 &pcfg_pull_none>,
- <4 1 3 &pcfg_pull_none>,
- <4 2 3 &pcfg_pull_none>,
- <4 3 3 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <4 RK_PA0 3 &pcfg_pull_none>,
+ <4 RK_PA5 3 &pcfg_pull_none>,
+ <4 RK_PA4 3 &pcfg_pull_none>,
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ <4 RK_PA2 3 &pcfg_pull_none>,
+ <4 RK_PA3 3 &pcfg_pull_none>;
};
};
spdif {
spdif_tx: spdif-tx {
- rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
};
};
};
-
- power: power-controller {
- compatible = "rockchip,rk3288-power-controller";
- #power-domain-cells = <1>;
- rockchip,pmu = <&pmu>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu {
- reg = <RK3288_PD_GPU>;
- clocks = <&cru ACLK_GPU>;
- };
-
- pd_hevc {
- reg = <RK3288_PD_HEVC>;
- clocks = <&cru ACLK_HEVC>,
- <&cru SCLK_HEVC_CABAC>,
- <&cru SCLK_HEVC_CORE>,
- <&cru HCLK_HEVC>;
- };
-
- pd_vio {
- reg = <RK3288_PD_VIO>;
- clocks = <&cru ACLK_IEP>,
- <&cru ACLK_ISP>,
- <&cru ACLK_RGA>,
- <&cru ACLK_VIP>,
- <&cru ACLK_VOP0>,
- <&cru ACLK_VOP1>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru HCLK_IEP>,
- <&cru HCLK_ISP>,
- <&cru HCLK_RGA>,
- <&cru HCLK_VIP>,
- <&cru HCLK_VOP0>,
- <&cru HCLK_VOP1>,
- <&cru PCLK_EDP_CTRL>,
- <&cru PCLK_HDMI_CTRL>,
- <&cru PCLK_LVDS_PHY>,
- <&cru PCLK_MIPI_CSI>,
- <&cru PCLK_MIPI_DSI0>,
- <&cru PCLK_MIPI_DSI1>,
- <&cru SCLK_EDP_24M>,
- <&cru SCLK_EDP>,
- <&cru SCLK_HDMI_CEC>,
- <&cru SCLK_HDMI_HDCP>,
- <&cru SCLK_ISP_JPE>,
- <&cru SCLK_ISP>,
- <&cru SCLK_RGA>;
- };
-
- pd_video {
- reg = <RK3288_PD_VIDEO>;
- clocks = <&cru ACLK_VCODEC>,
- <&cru HCLK_VCODEC>;
- };
- };
};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 08/15] arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (5 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 07/15] arm: dts: rockchip: sync rk3288.dtsi " Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 09/15] rockchip: fix boot_devices constants Johan Jonker
` (7 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
In order to sync rk3288.dtsi from Linux it needed to
move all u-boot specific properties in separate dtsi files.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-evb-u-boot.dtsi | 11 +++++
arch/arm/dts/rk3288-evb.dts | 11 -----
arch/arm/dts/rk3288-firefly-u-boot.dtsi | 31 +++++++++++++
arch/arm/dts/rk3288-firefly.dts | 17 -------
arch/arm/dts/rk3288-firefly.dtsi | 3 --
arch/arm/dts/rk3288-miqi-u-boot.dtsi | 20 +++++++++
arch/arm/dts/rk3288-miqi.dts | 11 -----
arch/arm/dts/rk3288-miqi.dtsi | 2 -
arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi | 44 +++++++++++++++++++
arch/arm/dts/rk3288-phycore-rdk.dts | 18 --------
arch/arm/dts/rk3288-phycore-som.dtsi | 6 ---
arch/arm/dts/rk3288-popmetal-u-boot.dtsi | 11 +++++
arch/arm/dts/rk3288-popmetal.dts | 11 -----
arch/arm/dts/rk3288-rock2-square-u-boot.dtsi | 30 +++++++++++++
arch/arm/dts/rk3288-rock2-square.dts | 18 --------
arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi | 14 ++++++
arch/arm/dts/rk3288-veyron-jerry.dts | 11 -----
arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi | 14 ++++++
arch/arm/dts/rk3288-veyron-mickey.dts | 11 -----
arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi | 14 ++++++
arch/arm/dts/rk3288-veyron-minnie.dts | 11 -----
arch/arm/dts/rk3288-veyron-u-boot.dtsi | 20 +++++++++
arch/arm/dts/rk3288-veyron.dtsi | 20 ---------
23 files changed, 209 insertions(+), 150 deletions(-)
create mode 100644 arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi
index 8ac7840f..c8f51207 100644
--- a/arch/arm/dts/rk3288-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi
@@ -5,6 +5,17 @@
#include "rk3288-u-boot.dtsi"
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x2>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
+};
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
index eac91a87..bb24a96c 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -15,17 +15,6 @@
};
};
-&dmc {
- rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
- 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
- 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
- 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
- 0x8 0x1f4>;
- rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
- 0x0 0xc3 0x6 0x2>;
- rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
-};
-
&pwm1 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
index 8b9c3831..c43d3281 100644
--- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
@@ -5,6 +5,37 @@
#include "rk3288-u-boot.dtsi"
+/ {
+ config {
+ u-boot,dm-pre-reloc;
+ u-boot,boot-led = "firefly:green:power";
+ };
+
+ leds {
+ u-boot,dm-pre-reloc;
+
+ work_led: led-0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ power_led: led-1 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ /* Add a dummy value to cause of-platdata think this is bytes */
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 1cff04e7..72982efd 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -13,23 +13,6 @@
chosen {
stdout-path = &uart2;
};
-
- config {
- u-boot,dm-pre-reloc;
- u-boot,boot-led = "firefly:green:power";
- };
-};
-
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&ir {
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index b7f279f7..1117d391 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -37,11 +37,9 @@
};
leds {
- u-boot,dm-pre-reloc;
compatible = "gpio-leds";
work {
- u-boot,dm-pre-reloc;
gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
@@ -50,7 +48,6 @@
};
power {
- u-boot,dm-pre-reloc;
gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";
diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
index 4f63fc9f..f2611aaa 100644
--- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
@@ -4,6 +4,26 @@
*/
#include "rk3288-u-boot.dtsi"
+/ {
+ leds {
+ u-boot,dm-pre-reloc;
+
+ work_led: led-0 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
&pinctrl {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
index e47170c6..4a2f249e 100644
--- a/arch/arm/dts/rk3288-miqi.dts
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -14,14 +14,3 @@
stdout-path = "serial2:115200n8";
};
};
-
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
-};
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
index 432f744b..cb80cbf2 100644
--- a/arch/arm/dts/rk3288-miqi.dtsi
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -34,11 +34,9 @@
leds {
- u-boot,dm-pre-reloc;
compatible = "gpio-leds";
work {
- u-boot,dm-pre-reloc;
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
label = "miqi:green:user";
linux,default-trigger = "default-on";
diff --git a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
new file mode 100644
index 00000000..30f4cb10
--- /dev/null
+++ b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3288-u-boot.dtsi"
+
+&dmc {
+ rockchip,num-channels = <2>;
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+
+ rk818: pmic@1c {
+ u-boot,dm-pre-reloc;
+
+ regulators {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
index cc392109..ebea8e67 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -112,19 +112,6 @@
};
};
-&dmc {
- rockchip,num-channels = <2>;
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
-};
-
&gmac {
status = "okay";
};
@@ -175,8 +162,6 @@
};
&pinctrl {
- u-boot,dm-pre-reloc;
-
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
bias-pull-up;
drive-strength = <12>;
@@ -246,8 +231,6 @@
};
&sdmmc {
- u-boot,dm-pre-reloc;
-
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -268,7 +251,6 @@
};
&uart2 {
- u-boot,dm-pre-reloc;
status = "okay";
};
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
index 02d11968..821525f7 100644
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -149,8 +149,6 @@
&emmc {
status = "okay";
- u-boot,dm-pre-reloc;
-
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
@@ -201,8 +199,6 @@
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
-
clock-frequency = <400000>;
rk818: pmic@1c {
@@ -216,7 +212,6 @@
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
vcc1-supply = <&vdd_sys>;
vcc2-supply = <&vdd_sys>;
@@ -230,7 +225,6 @@
vddio-supply = <&vdd_3v3_io>;
regulators {
- u-boot,dm-pre-reloc;
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
index 8ac7840f..3782253c 100644
--- a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
@@ -5,6 +5,17 @@
#include "rk3288-u-boot.dtsi"
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
&pinctrl {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
index 5c6d06f2..736dc51e 100644
--- a/arch/arm/dts/rk3288-popmetal.dts
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -15,17 +15,6 @@
};
};
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
-};
-
&pwm1 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
new file mode 100644
index 00000000..509f789b
--- /dev/null
+++ b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3288-u-boot.dtsi"
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+&gpio7 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 11c580a0..41676696 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -96,7 +96,6 @@
};
&sdmmc {
- u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -139,7 +138,6 @@
};
&pinctrl {
- u-boot,dm-pre-reloc;
ir {
ir_int: ir-int {
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -171,7 +169,6 @@
&uart2 {
status = "okay";
- u-boot,dm-pre-reloc;
reg-shift = <2>;
};
@@ -182,18 +179,3 @@
&usb_host0_ehci {
status = "okay";
};
-
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
-};
-
-&gpio7 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
new file mode 100644
index 00000000..2cc6b090
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3288-veyron-u-boot.dtsi"
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
index c251d9d5..ff7669eb 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -66,17 +66,6 @@
};
};
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
-};
-
&gpio_keys {
power {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
new file mode 100644
index 00000000..213a46ba
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3288-veyron-u-boot.dtsi"
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x2>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
+};
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
index e0dc3620..0521d9e0 100644
--- a/arch/arm/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/dts/rk3288-veyron-mickey.dts
@@ -161,17 +161,6 @@
};
};
-&dmc {
- rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
- 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
- 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
- 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
- 0x8 0x1f4>;
- rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
- 0x0 0xc3 0x6 0x2>;
- rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
-};
-
&emmc {
/delete-property/mmc-hs200-1_8v;
};
diff --git a/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
new file mode 100644
index 00000000..8211da41
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3288-veyron-u-boot.dtsi"
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x1>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
+};
diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts
index 646f6ae7..b56a3f4f 100644
--- a/arch/arm/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/dts/rk3288-veyron-minnie.dts
@@ -137,17 +137,6 @@
power-supply = <&backlight_regulator>;
};
-&dmc {
- rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
- 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
- 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
- 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
- 0x8 0x1f4>;
- rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
- 0x0 0xc3 0x6 0x1>;
- rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
-};
-
&emmc {
/delete-property/mmc-hs200-1_8v;
};
diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index 899fe6e7..2afbf96d 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -5,6 +5,26 @@
#include "rk3288-u-boot.dtsi"
+&dmc {
+ logic-supply = <&vdd_logic>;
+ rockchip,odt-disable-freq = <333000000>;
+ rockchip,dll-disable-freq = <333000000>;
+ rockchip,sr-enable-freq = <333000000>;
+ rockchip,pd-enable-freq = <666000000>;
+ rockchip,auto-self-refresh-cnt = <0>;
+ rockchip,auto-power-down-cnt = <64>;
+ rockchip,ddr-speed-bin = <21>;
+ rockchip,trcd = <10>;
+ rockchip,trp = <10>;
+ operating-points = <
+ /* KHz uV */
+ 200000 1050000
+ 333000 1100000
+ 533000 1150000
+ 666000 1200000
+ >;
+};
+
&gpio7 {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 8754043b..5dd0d5c4 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -220,26 +220,6 @@
cpu0-supply = <&vdd_cpu>;
};
-&dmc {
- logic-supply = <&vdd_logic>;
- rockchip,odt-disable-freq = <333000000>;
- rockchip,dll-disable-freq = <333000000>;
- rockchip,sr-enable-freq = <333000000>;
- rockchip,pd-enable-freq = <666000000>;
- rockchip,auto-self-refresh-cnt = <0>;
- rockchip,auto-power-down-cnt = <64>;
- rockchip,ddr-speed-bin = <21>;
- rockchip,trcd = <10>;
- rockchip,trp = <10>;
- operating-points = <
- /* KHz uV */
- 200000 1050000
- 333000 1100000
- 533000 1150000
- 666000 1200000
- >;
-};
-
&efuse {
status = "okay";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 09/15] rockchip: fix boot_devices constants
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (6 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 08/15] arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 10/15] arm: dts: rockchip: sync rk3288 DT boards from Linux Johan Jonker
` (6 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
The DT node name pattern in mmc-controller.yaml for mmc
is "^mmc(@.*)?$". The Rockchip mmc nodes have been synced
with Linux, so update the boot_devices constants as well.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/mach-rockchip/rk3188/rk3188.c | 4 ++--
arch/arm/mach-rockchip/rk322x/rk322x.c | 4 ++--
arch/arm/mach-rockchip/rk3288/rk3288.c | 4 ++--
arch/arm/mach-rockchip/rk3328/rk3328.c | 4 ++--
arch/arm/mach-rockchip/rk3368/rk3368.c | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
index 5a02914e..df8fa156 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -21,8 +21,8 @@
#define GRF_BASE 0x20008000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@10214000",
};
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
index ad4ac62e..a304795f 100644
--- a/arch/arm/mach-rockchip/rk322x/rk322x.c
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -9,8 +9,8 @@
#include <asm/arch-rockchip/hardware.h>
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@30020000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@30000000",
};
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index bc20bc5a..3ad28875 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -28,8 +28,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index ec3336cb..de17b886 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define FW_DDR_CON_REG 0xFF7C0040
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
- [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@ff500000",
};
static struct mm_region rk3328_mem_map[] = {
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index 9b7132d4..d0a6107e 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -58,8 +58,8 @@ static struct mm_region rk3368_mem_map[] = {
struct mm_region *mem_map = rk3368_mem_map;
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
#ifdef CONFIG_ARCH_EARLY_INIT_R
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 09/15] rockchip: fix boot_devices constants
2022-02-07 3:47 ` [PATCH v1 09/15] rockchip: fix boot_devices constants Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> The DT node name pattern in mmc-controller.yaml for mmc
> is "^mmc(@.*)?$". The Rockchip mmc nodes have been synced
> with Linux, so update the boot_devices constants as well.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> arch/arm/mach-rockchip/rk3188/rk3188.c | 4 ++--
> arch/arm/mach-rockchip/rk322x/rk322x.c | 4 ++--
> arch/arm/mach-rockchip/rk3288/rk3288.c | 4 ++--
> arch/arm/mach-rockchip/rk3328/rk3328.c | 4 ++--
> arch/arm/mach-rockchip/rk3368/rk3368.c | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 10/15] arm: dts: rockchip: sync rk3288 DT boards from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (7 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 09/15] rockchip: fix boot_devices constants Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 11/15] arm: dts: rockchip: rename mipi_dsi label in rk3288-evb.dtsi Johan Jonker
` (5 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
Sync rk3288 DT boards that have support both in
Linux 5.17 as in U-boot.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-firefly.dts | 17 +-
arch/arm/dts/rk3288-firefly.dtsi | 163 ++++++--
arch/arm/dts/rk3288-miqi.dts | 431 ++++++++++++++++++++-
arch/arm/dts/rk3288-phycore-rdk.dts | 109 +++---
arch/arm/dts/rk3288-phycore-som.dtsi | 143 ++-----
arch/arm/dts/rk3288-popmetal.dts | 505 ++++++++++++++++++++++++-
arch/arm/dts/rk3288-popmetal.dtsi | 547 ---------------------------
arch/arm/dts/rk3288-rock2-som.dtsi | 93 +++--
arch/arm/dts/rk3288-rock2-square.dts | 215 ++++++++---
arch/arm/dts/rk3288-tinker-s.dts | 9 +-
arch/arm/dts/rk3288-tinker.dts | 30 +-
arch/arm/dts/rk3288-tinker.dtsi | 407 ++++++++++----------
arch/arm/dts/rk3288-veyron.dtsi | 28 +-
13 files changed, 1582 insertions(+), 1115 deletions(-)
delete mode 100644 arch/arm/dts/rk3288-popmetal.dtsi
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 72982efd..313459da 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
*/
@@ -9,31 +9,22 @@
/ {
model = "Firefly-RK3288";
compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
};
&ir {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
};
&pinctrl {
act8846 {
pmic_vsel: pmic-vsel {
- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>;
};
};
ir {
ir_int: ir-int {
- rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
- usb_host {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index 1117d391..7fb58230 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -1,13 +1,36 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
*/
+#include <dt-bindings/input/input.h>
#include "rk3288.dtsi"
/ {
- memory {
- reg = <0 0x80000000>;
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ dovdd_1v8: dovdd-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dovdd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc28_dvp>;
};
ext_gmac: external-gmac-clock {
@@ -26,11 +49,11 @@
keys: gpio-keys {
compatible = "gpio-keys";
- button@0 {
- gpio-key,wakeup = <1>;
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ power {
+ wakeup-source;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
- linux,code = <116>;
+ linux,code = <KEY_POWER>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
};
@@ -39,24 +62,24 @@
leds {
compatible = "gpio-leds";
- work {
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ work_led: led-0 {
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
- pinctrl-0 = <&work_led>;
+ pinctrl-0 = <&work_led_pin>;
};
- power {
- gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
+ power_led: led-1 {
+ gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";
pinctrl-names = "default";
- pinctrl-0 = <&power_led>;
+ pinctrl-0 = <&power_led_pin>;
};
};
- vcc_sys: vsys-regulator {
+ vbat_wl: vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
@@ -67,7 +90,7 @@
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -98,7 +121,7 @@
vcc_host_5v: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host_5v";
@@ -111,7 +134,7 @@
vcc_otg_5v: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_5v";
@@ -120,6 +143,23 @@
regulator-always-on;
vin-supply = <&vcc_5v>;
};
+
+ /*
+ * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled
+ * by the dvp_pwr pin.
+ */
+ vcc28_dvp: vcc28-dvp-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dvp_pwr>;
+ regulator-name = "vcc28_dvp";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ };
};
&cpu0 {
@@ -127,12 +167,10 @@
};
&emmc {
- broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
@@ -150,12 +188,17 @@
phy-mode = "rgmii";
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
@@ -174,6 +217,8 @@
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
+ regulator-enable-ramp-delay = <300>;
+ regulator-ramp-delay = <8000>;
vin-supply = <&vcc_sys>;
};
@@ -195,7 +240,7 @@
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio7>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_int>;
};
@@ -207,6 +252,14 @@
pinctrl-0 = <&pmic_vsel>, <&pwr_hold>;
system-power-controller;
+ vp1-supply = <&vcc_sys>;
+ vp2-supply = <&vcc_sys>;
+ vp3-supply = <&vcc_sys>;
+ vp4-supply = <&vcc_sys>;
+ inl1-supply = <&vcc_sys>;
+ inl2-supply = <&vcc_sys>;
+ inl3-supply = <&vcc_20>;
+
regulators {
vcc_ddr: REG1 {
regulator-name = "vcc_ddr";
@@ -275,7 +328,7 @@
regulator-always-on;
};
- vcc_18: REG11 {
+ vccio_wl: vcc_18: REG11 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -308,6 +361,21 @@
status = "okay";
};
+&io_domains {
+ status = "okay";
+
+ audio-supply = <&vcca_33>;
+ bb-supply = <&vcc_io>;
+ dvp-supply = <&dovdd_1v8>;
+ flash0-supply = <&vcc_flash>;
+ flash1-supply = <&vcc_lan>;
+ gpio30-supply = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
+ lcdc-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vccio_wl>;
+};
+
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
@@ -324,43 +392,49 @@
act8846 {
pwr_hold: pwr-hold {
- rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
+ dvp {
+ dvp_pwr: dvp-pwr {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
phy_int: phy-int {
- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_pmeb: phy-pmeb {
- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rst: phy-rst {
- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
};
};
hym8563 {
rtc_int: rtc-int {
- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
keys {
pwr_key: pwr-key {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
- power_led: power-led {
- rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ power_led_pin: power-led-pin {
+ rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- work_led: work-led {
- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>;
+ work_led_pin: work-led-pin {
+ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -391,17 +465,17 @@
usb_host {
host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
usbhub_rst: usbhub-rst {
- rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
};
};
usb_otg {
otg_vbus_drv: otg-vbus-drv {
- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@@ -412,15 +486,14 @@
};
&sdio0 {
- broken-cd;
bus-width = <4>;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
- vmmc-supply = <&vcc_18>;
- status = "disabled";
+ vmmc-supply = <&vbat_wl>;
+ vqmmc-supply = <&vccio_wl>;
+ status = "okay";
};
&sdmmc {
@@ -429,10 +502,10 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
status = "okay";
};
@@ -442,6 +515,12 @@
status = "okay";
};
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
@@ -460,6 +539,10 @@
status = "okay";
};
+&usbphy {
+ status = "okay";
+};
+
&usb_host1 {
pinctrl-names = "default";
pinctrl-0 = <&usbhub_rst>;
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
index 4a2f249e..713f55e1 100644
--- a/arch/arm/dts/rk3288-miqi.dts
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -1,10 +1,11 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
-#include "rk3288-miqi.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3288.dtsi"
/ {
model = "mqmaker MiQi";
@@ -13,4 +14,428 @@
chosen {
stdout-path = "serial2:115200n8";
};
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ work_led: led-0 {
+ gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "miqi:green:user";
+ linux,default-trigger = "timer";
+ };
+ };
+
+ vcc_flash: flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_flash>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ vdd_cpu: syr827@40 {
+ compatible = "silergy,syr827";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x40>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <300>;
+ regulator-ramp-delay = <8000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_gpu: syr828@41 {
+ compatible = "silergy,syr828";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x41>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+
+ act8846: act8846@5a {
+ compatible = "active-semi,act8846";
+ reg = <0x5a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_vsel>;
+ system-power-controller;
+
+ vp1-supply = <&vcc_sys>;
+ vp2-supply = <&vcc_sys>;
+ vp3-supply = <&vcc_sys>;
+ vp4-supply = <&vcc_sys>;
+ inl1-supply = <&vcc_sys>;
+ inl2-supply = <&vcc_sys>;
+ inl3-supply = <&vcc_20>;
+
+ regulators {
+ vcc_ddr: REG1 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ };
+
+ vcc_io: REG2 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_log: REG3 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ vcc_20: REG4 {
+ regulator-name = "vcc_20";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ vccio_sd: REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd10_lcd: REG6 {
+ regulator-name = "vdd10_lcd";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vcca_18: REG7 {
+ regulator-name = "vcca_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcca_33: REG8 {
+ regulator-name = "vcca_33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_lan: REG9 {
+ regulator-name = "vcc_lan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_10: REG10 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ vcc_18: REG11 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc18_lcd: REG12 {
+ regulator-name = "vcc18_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ audio-supply = <&vcca_33>;
+ flash0-supply = <&vcc_flash>;
+ flash1-supply = <&vcc_lan>;
+ gpio30-supply = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
+ lcdc-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_18>;
+};
+
+&pinctrl {
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ act8846 {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ pmic_vsel: pmic-vsel {
+ rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ gmac {
+ phy_int: phy-int {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_pmeb: phy-pmeb {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rst: phy-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
+ sdmmc {
+ /*
+ * Default drive strength isn't enough to achieve even
+ * high-speed mode on firefly board so bump up to 12ma.
+ */
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ /*
+ * The otg controller is the only system power source,
+ * so needs to always stay in device mode.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
};
diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
index ebea8e67..1e33859d 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -1,60 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree file for Phytec PCM-947 carrier board
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/leds-pca9532.h>
#include "rk3288-phycore-som.dtsi"
/ {
model = "Phytec RK3288 PCM-947";
compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
- chosen {
- stdout-path = &uart2;
- };
-
user_buttons: user-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -155,6 +115,36 @@
&i2c4 {
status = "okay";
+
+ /* PCA9533 - 4-bit LED dimmer */
+ leddim: leddimmer@62 {
+ compatible = "nxp,pca9533";
+ reg = <0x62>;
+
+ led1 {
+ label = "red:user1";
+ linux,default-trigger = "none";
+ type = <PCA9532_TYPE_LED>;
+ };
+
+ led2 {
+ label = "green:user2";
+ linux,default-trigger = "none";
+ type = <PCA9532_TYPE_LED>;
+ };
+
+ led3 {
+ label = "blue:user3";
+ linux,default-trigger = "none";
+ type = <PCA9532_TYPE_LED>;
+ };
+
+ led4 {
+ label = "red:user4";
+ linux,default-trigger = "none";
+ type = <PCA9532_TYPE_LED>;
+ };
+ };
};
&i2c5 {
@@ -170,15 +160,15 @@
buttons {
user_button_pins: user-button-pins {
/* button 1 */
- rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
+ rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
/* button 2 */
- <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+ <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rv4162 {
i2c_rtc_int: i2c-rtc-int {
- rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -188,44 +178,44 @@
* high-speed mode on pcm-947 board so bump up to 12 mA.
*/
sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
};
sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touchscreen {
ts_irq_pin: ts-irq-pin {
- rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host0_vbus_drv: host0-vbus-drv {
- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
host1_vbus_drv: host1-vbus-drv {
- rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_otg {
otg_vbus_drv: otg-vbus-drv {
- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@@ -236,10 +226,13 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vdd_io_sd>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
index 821525f7..db463d2f 100644
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree file for Phytec phyCORE-RK3288 SoM
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/net/ti-dp83867.h>
@@ -55,13 +18,12 @@
*/
memory {
device_type = "memory";
- reg = <0 0x8000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rk818;
- eeprom0 = &i2c_eeprom_id;
};
ext_gmac: external-gmac-clock {
@@ -71,28 +33,12 @@
clock-output-names = "ext_gmac";
};
- io_domains: io_domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
-
- status = "okay";
- sdcard-supply = <&vdd_io_sd>;
- flash0-supply = <&vdd_emmc_io>;
- flash1-supply = <&vdd_misc_1v8>;
- gpio1830-supply = <&vdd_3v3_io>;
- gpio30-supply = <&vdd_3v3_io>;
- bb-supply = <&vdd_3v3_io>;
- dvp-supply = <&vdd_3v3_io>;
- lcdc-supply = <&vdd_3v3_io>;
- wifi-supply = <&vdd_3v3_io>;
- audio-supply = <&vdd_3v3_io>;
- };
-
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&user_led>;
+ pinctrl-0 = <&user_led_pin>;
- user {
+ user_led: led-0 {
label = "green_led";
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -127,33 +73,12 @@
};
};
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
- operating-points = <
- /* KHz uV */
- 1800000 1400000
- 1608000 1350000
- 1512000 1300000
- 1416000 1200000
- 1200000 1100000
- 1008000 1050000
- 816000 1000000
- 696000 950000
- 600000 900000
- 408000 900000
- 312000 900000
- 216000 900000
- 126000 900000
- >;
-};
-
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vdd_3v3_io>;
@@ -189,6 +114,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
};
};
@@ -197,12 +123,25 @@
ddc-i2c-bus = <&i2c5>;
};
+&io_domains {
+ status = "okay";
+ sdcard-supply = <&vdd_io_sd>;
+ flash0-supply = <&vdd_emmc_io>;
+ flash1-supply = <&vdd_misc_1v8>;
+ gpio1830-supply = <&vdd_3v3_io>;
+ gpio30-supply = <&vdd_3v3_io>;
+ bb-supply = <&vdd_3v3_io>;
+ dvp-supply = <&vdd_3v3_io>;
+ lcdc-supply = <&vdd_3v3_io>;
+ wifi-supply = <&vdd_3v3_io>;
+ audio-supply = <&vdd_3v3_io>;
+};
+
&i2c0 {
status = "okay";
clock-frequency = <400000>;
rk818: pmic@1c {
- status = "okay";
compatible = "rockchip,rk818";
reg = <0x1c>;
interrupt-parent = <&gpio0>;
@@ -361,11 +300,10 @@
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
+ regulator-off-in-suspend;
};
};
};
@@ -378,13 +316,6 @@
pagesize = <32>;
};
- /* M24C32-D Identification page */
- i2c_eeprom_id: eeprom@58 {
- compatible = "atmel,24c32";
- reg = <0x58>;
- pagesize = <32>;
- };
-
vdd_cpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
@@ -411,49 +342,49 @@
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA1 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA2 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA3 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA4 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA5 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA6 2 &pcfg_pull_none_12ma>,
+ <3 RK_PA7 2 &pcfg_pull_none_12ma>;
};
};
gmac {
phy_int: phy-int {
- rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rst: phy-rst {
- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
};
};
leds {
- user_led: user-led {
- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
+ user_led_pin: user-led-pin {
+ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>;
};
};
pmic {
pmic_int: pmic-int {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
/* Pin for switching state between sleep and non-sleep state */
pmic_sleep: pmic-sleep {
- rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
index 736dc51e..8c7376d6 100644
--- a/arch/arm/dts/rk3288-popmetal.dts
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -1,20 +1,513 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2014, 2015 Andy Yan <andy.yan@rock-chips.com>
*/
/dts-v1/;
-#include "rk3288-popmetal.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3288.dtsi"
/ {
model = "PopMetal-RK3288";
compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
- chosen {
- stdout-path = &uart2;
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ wakeup-source;
+ debounce-interval = <100>;
+ };
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ vcc_flash: flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled
+ * by the dvp_pwr pin.
+ */
+ vcc18_dvp: vcc18-dvp-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc18-dvp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc28_dvp>;
+ };
+
+ vcc28_dvp: vcc28-dvp-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dvp_pwr>;
+ regulator-name = "vcc28_dvp";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_flash>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp; /* wp not hooked up */
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&gmac {
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_18>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_io>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lan: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_lan";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ ldo5: LDO_REG5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "ldo5";
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_33: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcca_33";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_wl: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vccio_wl";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_lcd: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ak8963: ak8963@d {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0d>;
+ interrupt-parent = <&gpio8>;
+ interrupts = <RK_PA1 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&comp_int>;
+ vdd-supply = <&vcc_io>;
+ vid-supply = <&vcc_io>;
+ };
+
+ l3g4200d: l3g4200d@69 {
+ compatible = "st,l3g4200d-gyro";
+ st,drdy-int-pin = <2>;
+ reg = <0x69>;
+ vdd-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+ };
+
+ mma8452: mma8452@1d {
+ compatible = "fsl,mma8452";
+ reg = <0x1d>;
+ interrupt-parent = <&gpio8>;
+ interrupts = <RK_PA0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsensor_int>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ audio-supply = <&vcca_33>;
+ bb-supply = <&vcc_io>;
+ dvp-supply = <&vcc18_dvp>;
+ flash0-supply = <&vcc_flash>;
+ flash1-supply = <&vcc_lan>;
+ gpio30-supply = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
+ lcdc-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vccio_wl>;
+};
+
+&pinctrl {
+ ak8963 {
+ comp_int: comp-int {
+ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ dvp {
+ dvp_pwr: dvp-pwr {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ mma8452 {
+ gsensor_int: gsensor-int {
+ rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
};
-&pwm1 {
+&usb_otg {
status = "okay";
};
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi
deleted file mode 100644
index 63785eb5..00000000
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "rk3288.dtsi"
-
-/ {
- memory{
- device_type = "memory";
- reg = <0 0x80000000>;
- };
-
- ext_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "ext_gmac";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,input-type = <1>;
- wakeup-source;
- debounce-interval = <100>;
- };
- };
-
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <&grf>;
-
- audio-supply = <&vcca_33>;
- bb-supply = <&vcc_io>;
- dvp-supply = <&vcc18_dvp>;
- flash0-supply = <&vcc_flash>;
- flash1-supply = <&vcc_lan>;
- gpio30-supply = <&vcc_io>;
- gpio1830-supply = <&vcc_io>;
- lcdc-supply = <&vcc_io>;
- sdcard-supply = <&vccio_sd>;
- wifi-supply = <&vccio_wl>;
- };
-
- ir: ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_int>;
- };
-
- vcc_flash: flash-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_flash";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_io>;
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwr>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <100000>;
- vin-supply = <&vcc_io>;
- };
-
- vcc_sys: vsys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /*
- * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled
- * by the dvp_pwr pin.
- */
- vcc18_dvp: vcc18-dvp-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc18-dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc28_dvp>;
- };
-
- vcc28_dvp: vcc28-dvp-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&dvp_pwr>;
- regulator-name = "vcc28_dvp";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- vin-supply = <&vcc_io>;
- };
-
- vcc5v0_host: usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-name = "vcc5v0_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- disable-wp;
- non-removable;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc_flash>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&gmac {
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
- assigned-clocks = <&cru SCLK_MAC>;
- assigned-clock-parents = <&ext_gmac>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c5>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <400000>;
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int &global_pwroff>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_18>;
- vcc9-supply = <&vcc_io>;
- vcc10-supply = <&vcc_io>;
- vcc11-supply = <&vcc_sys>;
- vcc12-supply = <&vcc_io>;
- vddio-supply = <&vcc_io>;
-
- regulators {
- vdd_cpu: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_arm";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-name = "vdd_gpu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_ddr";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_io";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lan: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_lan";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vdd_10";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc18_lcd: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_lcd";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- ldo5: LDO_REG5 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "ldo5";
- };
-
- vdd10_lcd: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vdd10_lcd";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_18: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_18";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca_33: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcca_33";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_wl: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vccio_wl";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_lcd: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_lcd";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <400000>;
-
- ak8963: ak8963@0d {
- compatible = "asahi-kasei,ak8975";
- reg = <0x0d>;
- interrupt-parent = <&gpio8>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&comp_int>;
- };
-
- l3g4200d: l3g4200d@68 {
- compatible = "st,l3g4200d-gyro";
- st,drdy-int-pin = <2>;
- reg = <0x6b>;
- };
-
- mma8452: mma8452@1d {
- compatible = "fsl,mma8452";
- reg = <0x1d>;
- interrupt-parent = <&gpio8>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&gsensor_int>;
- };
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2c4 {
- status = "okay";
-};
-
-&i2c5 {
- status = "okay";
-};
-
-&pinctrl {
- ak8963 {
- comp_int: comp-int {
- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- dvp {
- dvp_pwr: dvp-pwr {
- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- ir {
- ir_int: ir-int {
- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- mma8452 {
- gsensor_int: gsensor-int {
- rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb_host {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&saradc {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-&usb_host1 {
- vbus-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3288-rock2-som.dtsi b/arch/arm/dts/rk3288-rock2-som.dtsi
index 1ece66f3..76363b8a 100644
--- a/arch/arm/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/dts/rk3288-rock2-som.dtsi
@@ -1,49 +1,11 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/pwm/pwm.h>
#include "rk3288.dtsi"
/ {
- memory {
- reg = <0x0 0x80000000>;
+ memory@0 {
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
@@ -51,7 +13,7 @@
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
};
ext_gmac: external-gmac-clock {
@@ -61,6 +23,15 @@
clock-output-names = "ext_gmac";
};
+ vcc_flash: flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <150>;
+ vin-supply = <&vcc_io>;
+ };
+
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -80,11 +51,11 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
mmc-pwrseq = <&emmc_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_flash>;
status = "okay";
};
@@ -96,13 +67,18 @@
phy-supply = <&vccio_pmu>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins &phy_rst>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
rx_delay = <0x10>;
tx_delay = <0x30>;
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -126,7 +102,7 @@
regulator-always-on;
};
- vcc_io: REG2 {
+ vcc_io: vccio_codec: REG2 {
regulator-name = "VCC_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -233,24 +209,43 @@
};
};
+&io_domains {
+ status = "okay";
+
+ audio-supply = <&vcc_io>;
+ bb-supply = <&vcc_io>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc_flash>;
+ flash1-supply = <&vccio_pmu>;
+ gpio30-supply = <&vccio_pmu>;
+ gpio1830-supply = <&vcc_io>;
+ lcdc-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_18>;
+};
+
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>;
- };
+ emmc_reset: emmc-reset {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
gmac {
phy_rst: phy-rst {
- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
};
};
};
+&saradc {
+ vref-supply = <&vcc_18>;
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 41676696..c4d1d142 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -1,44 +1,7 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "rk3288-rock2-som.dtsi"
/ {
@@ -49,9 +12,51 @@
stdout-path = "serial2:115200n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ heartbeat_led: led-0 {
+ gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "rock2:green:state1";
+ linux,default-trigger = "heartbeat";
+ };
+
+ mmc_led: led-1 {
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "rock2:blue:state2";
+ linux,default-trigger = "mmc0";
+ };
+ };
+
ir: ir-receiver {
compatible = "gpio-ir-receiver";
- gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_int>;
};
@@ -65,27 +70,56 @@
};
};
+ sata_pwr: sata-prw-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata_pwr_en>;
+ /* Always turn on the 5V sata power connector */
+ regulator-always-on;
+ regulator-name = "sata_pwr";
+ };
+
spdif_out: spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
+ sound-i2s {
+ compatible = "rockchip,rk3288-hdmi-analog";
+ pinctrl-names = "default";
+ pinctrl-0 = <&phone_ctl>, <&hp_det>;
+ rockchip,audio-codec = <&es8388>;
+ rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+ rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,model = "I2S";
+ rockchip,routing = "Analog", "LOUT2",
+ "Analog", "ROUT2";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+
vcc_usb_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
- /* Always on as the rockchip usb phy doesn't have a vbus-supply
- * property
- */
- regulator-always-on;
regulator-name = "vcc_host";
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
regulator-name = "vcc_sd";
@@ -95,13 +129,25 @@
};
};
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18>;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
@@ -119,63 +165,124 @@
};
&i2c0 {
- hym8563@51 {
+ hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
};
};
+&i2c2 {
+ status = "okay";
+
+ es8388: es8388@10 {
+ compatible = "everest,es8388", "everest,es8328";
+ reg = <0x10>;
+ AVDD-supply = <&vccio_codec>;
+ DVDD-supply = <&vccio_codec>;
+ HPVDD-supply = <&vccio_codec>;
+ PVDD-supply = <&vccio_codec>;
+ clocks = <&cru SCLK_I2S0_OUT>;
+ };
+};
+
&i2c5 {
status = "okay";
};
+&i2s {
+ status = "okay";
+};
+
&pinctrl {
ir {
ir_int: ir-int {
- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int: pmic-int {
- rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ phone_ctl: phone-ctl {
+ rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sata {
+ sata_pwr_en: sata-pwr-en {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ wifi_enable: wifi-enable {
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
+&saradc {
+ status = "okay";
+};
+
&spdif {
status = "okay";
};
&uart2 {
status = "okay";
- reg-shift = <2>;
};
&usbphy {
status = "okay";
};
+&usbphy1 {
+ vbus-supply = <&vcc_usb_host>;
+};
+
&usb_host0_ehci {
status = "okay";
};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3288-tinker-s.dts b/arch/arm/dts/rk3288-tinker-s.dts
index cc7ac5f8..970e1385 100644
--- a/arch/arm/dts/rk3288-tinker-s.dts
+++ b/arch/arm/dts/rk3288-tinker-s.dts
@@ -10,10 +10,6 @@
/ {
model = "Rockchip RK3288 Asus Tinker Board S";
compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
};
&emmc {
@@ -27,3 +23,8 @@
mmc-ddr-1_8v;
status = "okay";
};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
+};
diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts
index 8b1848c3..1e43527a 100644
--- a/arch/arm/dts/rk3288-tinker.dts
+++ b/arch/arm/dts/rk3288-tinker.dts
@@ -1,33 +1,13 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
+
#include "rk3288-tinker.dtsi"
/ {
- model = "Tinker-RK3288";
- compatible = "rockchip,rk3288-tinker", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
-};
-
-&pinctrl {
- usb {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&usb_host1 {
- vbus-supply = <&vcc5v0_host>;
- status = "okay";
+ model = "Rockchip RK3288 Asus Tinker Board";
+ compatible = "asus,rk3288-tinker", "rockchip,rk3288";
};
diff --git a/arch/arm/dts/rk3288-tinker.dtsi b/arch/arm/dts/rk3288-tinker.dtsi
index 2f816af4..9c1e38c5 100644
--- a/arch/arm/dts/rk3288-tinker.dtsi
+++ b/arch/arm/dts/rk3288-tinker.dtsi
@@ -1,70 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/rockchip,rk808.h>
/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
memory {
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
- reg = <0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
- #clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
button@0 {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
- gpio-key,wakeup = <1>;
+ wakeup-source;
debounce-interval = <100>;
};
};
@@ -72,14 +46,44 @@
gpio-leds {
compatible = "gpio-leds";
- pwr-led {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ act_led: led-0 {
+ gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ heartbeat_led: led-1 {
+ gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ pwr_led: led-2 {
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
+ };
- act-led {
- gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger="mmc0";
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable>;
+ reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>,
+ <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,tinker-codec";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
};
};
@@ -92,11 +96,6 @@
regulator-boot-on;
};
- /*
- * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
- * vcc_io directly. Those boards won't be able to power cycle SD cards
- * but it shouldn't hurt to toggle this pin there anyway.
- */
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
@@ -108,80 +107,66 @@
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
-
- vcc5v0_host: usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-name = "vcc5v0_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp; /* wp not hooked up */
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- status = "okay";
- supports-sd;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+&cpu_opp_table {
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1400000>;
+ };
};
&gmac {
- phy-supply = <&vcc33_lan>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio4 7 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ phy-supply = <&vcc33_lan>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
};
&i2c0 {
- status = "okay";
clock-frequency = <400000>;
+ status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int &global_pwroff>;
+ pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
rockchip,system-power-controller;
wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
@@ -189,20 +174,21 @@
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_18>;
+ vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_io>;
vcc10-supply = <&vcc_io>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
- vddio-supply = <&vcc18_ldo1>;
+ vddio-supply = <&vcc_io>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm";
+ regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -214,6 +200,7 @@
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -359,47 +346,149 @@
&i2c2 {
status = "okay";
- headset: nau8825@1a {
- compatible = "nuvoton,nau8825";
- #sound-dai-cells = <0>;
- reg = <0x1a>;
- interrupt-parent = <&gpio6>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- nuvoton,jkdet-enable = <1>;
- nuvoton,jkdet-pull-enable = <1>;
- nuvoton,jkdet-pull-up = <0>;
- nuvoton,jkdet-polarity = <1>;
- nuvoton,vref-impedance = <2>;
- nuvoton,micbias-voltage = <6>;
- nuvoton,sar-threshold-num = <4>;
- nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>;
- nuvoton,sar-hysteresis = <0>;
- nuvoton,sar-voltage = <6>;
- nuvoton,sar-compare-time = <0>;
- nuvoton,sar-sampling-time = <0>;
- nuvoton,short-key-debounce = <3>;
- nuvoton,jack-insert-debounce = <7>;
- nuvoton,jack-eject-debounce = <7>;
- clock-names = "mclk";
- clocks = <&cru SCLK_I2S0_OUT>;
- };
};
&i2c5 {
status = "okay";
};
-&wdt {
+&i2s {
+ #sound-dai-cells = <0>;
status = "okay";
};
+&io_domains {
+ status = "okay";
+
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_18>;
+};
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ backlight {
+ bl_en: bl-en {
+ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ eth_phy {
+ eth_phy_pwr: eth-phy-pwr {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ dvs_1: dvs-1 {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pwr_3g: pwr-3g {
+ rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ wifi_enable: wifi-enable {
+ rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
&pwm0 {
status = "okay";
};
&saradc {
vref-supply = <&vcc18_ldo1>;
- status ="okay";
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ broken-cd;
+ disable-wp; /* wp not hooked up */
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+ vmmc-supply = <&vcc33_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "okay";
};
&uart0 {
@@ -422,12 +511,6 @@
status = "okay";
};
-&tsadc {
- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
- status = "okay";
-};
-
&usbphy {
status = "okay";
};
@@ -441,7 +524,7 @@
};
&usb_otg {
- status= "okay";
+ status = "okay";
};
&vopb {
@@ -460,72 +543,6 @@
status = "okay";
};
-&pinctrl {
- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
- drive-strength = <8>;
- };
-
- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- backlight {
- bl_en: bl-en {
- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- eth_phy {
- eth_phy_pwr: eth-phy-pwr {
- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- /*
- * Default drive strength isn't enough to achieve even
- * high-speed mode on EVB board so bump up to 8ma.
- */
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
- };
-
- sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pwr_3g: pwr-3g {
- rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+&wdt {
+ status = "okay";
};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 5dd0d5c4..0e074c32 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -199,21 +199,6 @@
/* Faux input supply. See bt_regulator description. */
vin-supply = <&bt_regulator>;
};
-
- io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <&grf>;
-
- audio-supply = <&vcc18_codec>;
- bb-supply = <&vcc33_io>;
- dvp-supply = <&vcc_18>;
- flash0-supply = <&vcc18_flashio>;
- gpio1830-supply = <&vcc33_io>;
- gpio30-supply = <&vcc33_io>;
- lcdc-supply = <&vcc33_lcd>;
- sdcard-supply = <&vccio_sd>;
- wifi-supply = <&vcc18_wl>;
- };
};
&cpu0 {
@@ -508,6 +493,19 @@
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
};
+&io_domains {
+ audio-supply = <&vcc18_codec>;
+ bb-supply = <&vcc33_io>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc18_flashio>;
+ gpio1830-supply = <&vcc33_io>;
+ gpio30-supply = <&vcc33_io>;
+ lcdc-supply = <&vcc33_lcd>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc18_wl>;
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 11/15] arm: dts: rockchip: rename mipi_dsi label in rk3288-evb.dtsi
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (8 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 10/15] arm: dts: rockchip: sync rk3288 DT boards from Linux Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 12/15] arm: dts: rockchip: remove hdmi_audio node from rk3288-veyron.dtsi Johan Jonker
` (4 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
The rk3288 mipi_dsi node in sync with Linux rk3288.dtsi
has a different label then in use by rk3288-evb.dtsi,
so fix compile and rename label.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-evb.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
index 04902c0b..72da8847 100644
--- a/arch/arm/dts/rk3288-evb.dtsi
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -448,7 +448,7 @@
status = "okay";
};
-&mipi_dsi0 {
+&mipi_dsi {
status = "disabled";
rockchip,panel = <&panel>;
display-timings {
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 11/15] arm: dts: rockchip: rename mipi_dsi label in rk3288-evb.dtsi
2022-02-07 3:47 ` [PATCH v1 11/15] arm: dts: rockchip: rename mipi_dsi label in rk3288-evb.dtsi Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> The rk3288 mipi_dsi node in sync with Linux rk3288.dtsi
> has a different label then in use by rk3288-evb.dtsi,
> so fix compile and rename label.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> arch/arm/dts/rk3288-evb.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
If this actually breaks something you should merge this patch with the
one that broke it, so people can bisect the build.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 12/15] arm: dts: rockchip: remove hdmi_audio node from rk3288-veyron.dtsi
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (9 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 11/15] arm: dts: rockchip: rename mipi_dsi label in rk3288-evb.dtsi Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` Simon Glass
2022-02-07 3:47 ` [PATCH v1 13/15] arm: dts: rockchip: move all rk3288-veyron u-boot related properties Johan Jonker
` (3 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
The hdmi_audio node doesn't exists in rk3288.dtsi in sync with Linux.
Fix compile by removal of the hdmi_audio node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-veyron.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 0e074c32..cd0e7362 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -564,10 +564,6 @@
status = "okay";
};
-&hdmi_audio {
- status = "okay";
-};
-
&gpu {
status = "okay";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 12/15] arm: dts: rockchip: remove hdmi_audio node from rk3288-veyron.dtsi
2022-02-07 3:47 ` [PATCH v1 12/15] arm: dts: rockchip: remove hdmi_audio node from rk3288-veyron.dtsi Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
0 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> The hdmi_audio node doesn't exists in rk3288.dtsi in sync with Linux.
> Fix compile by removal of the hdmi_audio node.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> arch/arm/dts/rk3288-veyron.dtsi | 4 ----
> 1 file changed, 4 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
Same comment about bisectability
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index 0e074c32..cd0e7362 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -564,10 +564,6 @@
> status = "okay";
> };
>
> -&hdmi_audio {
> - status = "okay";
> -};
> -
> &gpu {
> status = "okay";
> };
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v1 13/15] arm: dts: rockchip: move all rk3288-veyron u-boot related properties
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (10 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 12/15] arm: dts: rockchip: remove hdmi_audio node from rk3288-veyron.dtsi Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 14/15] arm: dts: rockchip: sync rk3288-veyron DT from Linux Johan Jonker
` (2 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
In order to sync rk3288-veyron related DT files
all u-boot properties have to move to rk3288-veyron-u-boot.dtsi
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-veyron-u-boot.dtsi | 42 ++++++++++++++++++++++++++
arch/arm/dts/rk3288-veyron.dtsi | 19 ------------
2 files changed, 42 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index 2afbf96d..c8b33fea 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -5,6 +5,12 @@
#include "rk3288-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = &spi_flash;
+ };
+};
+
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;
@@ -25,7 +31,43 @@
>;
};
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
&gpio7 {
u-boot,dm-pre-reloc;
};
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&rk808 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi2 {
+ u-boot,dm-pre-reloc;
+};
+
+&spi_flash {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index cd0e7362..434b0d49 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -16,7 +16,6 @@
chosen {
stdout-path = &uart2;
- u-boot,spl-boot-order = &spi_flash;
};
firmware {
@@ -264,10 +263,8 @@
&spi2 {
status = "okay";
- u-boot,dm-pre-reloc;
spi_flash: spiflash@0 {
- u-boot,dm-pre-reloc;
compatible = "spidev", "jedec,spi-nor";
spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
reg = <0>;
@@ -280,7 +277,6 @@
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
i2c-scl-rising-time-ns = <100>; /* 45ns measured */
- u-boot,dm-pre-reloc;
rk808: pmic@1b {
compatible = "rockchip,rk808";
@@ -293,7 +289,6 @@
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
vcc1-supply = <&vcc33_sys>;
vcc2-supply = <&vcc33_sys>;
@@ -535,7 +530,6 @@
&uart2 {
status = "okay";
- u-boot,dm-pre-reloc;
reg-shift = <2>;
};
@@ -575,7 +569,6 @@
};
&pinctrl {
- u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
@@ -800,15 +793,3 @@
assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
assigned-clock-parents = <&cru SCLK_OTGPHY0>;
};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
-};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 14/15] arm: dts: rockchip: sync rk3288-veyron DT from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (11 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 13/15] arm: dts: rockchip: move all rk3288-veyron u-boot related properties Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-07 3:47 ` [PATCH v1 15/15] arm: dts: rockchip: rk3288-evb: fix memory reg value Johan Jonker
2022-02-26 18:36 ` [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Simon Glass
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
Sync rk3288-veyron DT from Linux version 5.17.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-veyron-analog-audio.dtsi | 99 +++
.../dts/rk3288-veyron-broadcom-bluetooth.dtsi | 22 +
arch/arm/dts/rk3288-veyron-chromebook.dtsi | 115 ++--
arch/arm/dts/rk3288-veyron-edp.dtsi | 141 ++++
arch/arm/dts/rk3288-veyron-jerry.dts | 512 ++++++++++----
arch/arm/dts/rk3288-veyron-mickey.dts | 343 +++++++---
arch/arm/dts/rk3288-veyron-minnie.dts | 441 +++++++-----
arch/arm/dts/rk3288-veyron-sdmmc.dtsi | 89 +++
arch/arm/dts/rk3288-veyron-speedy.dts | 303 ++++++--
arch/arm/dts/rk3288-veyron.dtsi | 644 ++++++------------
10 files changed, 1799 insertions(+), 910 deletions(-)
create mode 100644 arch/arm/dts/rk3288-veyron-analog-audio.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-edp.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-sdmmc.dtsi
diff --git a/arch/arm/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/dts/rk3288-veyron-analog-audio.dtsi
new file mode 100644
index 00000000..51208d16
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-analog-audio.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Google Veyron (and derivatives) fragment for the max98090 audio
+ * codec and analog headphone jack.
+ *
+ * Copyright 2016 Google, Inc
+ */
+
+/ {
+ sound {
+ compatible = "rockchip,rockchip-audio-max98090";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mic_det>, <&hp_det>;
+ rockchip,model = "VEYRON-I2S";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&max98090>;
+ rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
+ rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
+ rockchip,headset-codec = <&headsetcodec>;
+ rockchip,hdmi-codec = <&hdmi>;
+ };
+};
+
+&i2c2 {
+ max98090: max98090@10 {
+ compatible = "maxim,max98090";
+ reg = <0x10>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S0_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&int_codec>;
+ };
+};
+
+&i2c4 {
+ headsetcodec: ts3a227e@3b {
+ compatible = "ti,ts3a227e";
+ reg = <0x3b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts3a227e_int_l>;
+ ti,micbias = <7>; /* MICBIAS = 2.8V */
+ };
+};
+
+&i2s {
+ status = "okay";
+};
+
+&io_domains {
+ audio-supply = <&vcc18_codec>;
+};
+
+&rk808 {
+ vcc10-supply = <&vcc33_sys>;
+
+ regulators {
+ vcc18_codec: LDO_REG6 {
+ regulator-name = "vcc18_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ codec {
+ hp_det: hp-det {
+ rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ /*
+ * HACK: We're going to _pull down_ this _active low_ interrupt
+ * so that it never fires. We don't need this interrupt because
+ * we've got a ts3a227e chip but the driver requires it.
+ */
+ int_codec: int-codec {
+ rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ mic_det: mic-det {
+ rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headset {
+ ts3a227e_int_l: ts3a227e-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
new file mode 100644
index 00000000..a10d25ac
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
+ * chip.
+ *
+ * Copyright 2019 Google, Inc
+ */
+
+&uart0 {
+ bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
+ <&bt_dev_wake>;
+
+ compatible = "brcm,bcm43540-bt";
+ host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+};
diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index 143eaae2..05112c25 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -1,39 +1,45 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron (and derivatives) board device tree source
+ * Chromebook specific parts
*
- * Copyright 2014 Google, Inc
+ * Copyright 2015 Google, Inc
*/
#include <dt-bindings/clock/rockchip,rk808.h>
#include <dt-bindings/input/input.h>
#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-analog-audio.dtsi"
+#include "rk3288-veyron-edp.dtsi"
+#include "rk3288-veyron-sdmmc.dtsi"
/ {
aliases {
+ /* Assign 20 so we don't get confused w/ builtin ones */
i2c20 = &i2c_tunnel;
- video0 = &vopl;
- video1 = &vopb;
- };
-
- gpio_keys: gpio-keys {
- pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
- lid {
- label = "Lid";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- linux,code = <0>; /* SW_LID */
- linux,input-type = <5>; /* EV_SW */
- debounce-interval = <1>;
- gpio-key,wakeup;
- };
};
gpio-charger {
compatible = "gpio-charger";
- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ charger-type = "mains";
+ gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ac_present_ap>;
- charger-type = "mains";
+ };
+
+ lid_switch: lid-switch {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_lid_int_l>;
+
+ lid {
+ label = "Lid";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ debounce-interval = <1>;
+ };
};
/* A non-regulated voltage from power supply or battery */
@@ -56,7 +62,7 @@
vcc5_host1: vcc5-host1-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host1_pwr_en>;
regulator-name = "vcc5_host1";
@@ -68,7 +74,7 @@
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usbotg_pwren_h>;
regulator-name = "vcc5_host2";
@@ -78,34 +84,34 @@
};
&rk808 {
+ vcc11-supply = <&vcc_5v>;
+
regulators {
vcc33_ccd: LDO_REG8 {
+ regulator-name = "vcc33_ccd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_ccd";
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
};
};
&spi0 {
status = "okay";
- spi-activate-delay = <100>;
- spi-max-frequency = <3000000>;
- spi-deactivate-delay = <200>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
- spi-max-frequency = <3000000>;
+ reg = <0>;
+ google,cros-ec-spi-pre-delay = <30>;
interrupt-parent = <&gpio7>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_int>;
- reg = <0>;
- google,cros-ec-spi-pre-delay = <30>;
+ spi-max-frequency = <3000000>;
i2c_tunnel: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
@@ -118,86 +124,59 @@
&i2c4 {
trackpad@15 {
- compatible = "elan,i2c_touchpad";
+ compatible = "elan,ekth3000";
+ reg = <0x15>;
interrupt-parent = <&gpio7>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int>;
- reg = <0x15>;
vcc-supply = <&vcc33_io>;
wakeup-source;
};
};
&pinctrl {
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &suspend_l_wake
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &suspend_l_sleep
- &bt_dev_wake_sleep
- >;
-
buttons {
ap_lid_int_l: ap-lid-int-l {
- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
charger {
ac_present_ap: ac-present-ap {
- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cros-ec {
ec_int: ec-int {
- rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- sdmmc_wp_gpio: sdmmc-wp-gpio {
- rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
suspend {
suspend_l_wake: suspend-l-wake {
- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
};
suspend_l_sleep: suspend-l-sleep {
- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
};
};
trackpad {
trackpad_int: trackpad-int {
- rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb-host {
host1_pwr_en: host1-pwr-en {
- rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
usbotg_pwren_h: usbotg-pwren-h {
- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/dts/rk3288-veyron-edp.dtsi b/arch/arm/dts/rk3288-veyron-edp.dtsi
new file mode 100644
index 00000000..32c0f107
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-edp.dtsi
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron (and derivatives) fragment for the edp displays
+ *
+ * Copyright 2019 Google LLC
+ */
+
+/ {
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+
+ panel_regulator: panel-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <128>;
+ enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en>;
+ pwms = <&pwm0 0 1000000 0>;
+ post-pwm-on-delay-ms = <10>;
+ pwm-off-delay-ms = <10>;
+ power-supply = <&backlight_regulator>;
+ };
+
+ panel: panel {
+ compatible = "innolux,n116bge";
+ status = "okay";
+ power-supply = <&panel_regulator>;
+ backlight = <&backlight>;
+
+ panel-timing {
+ clock-frequency = <74250000>;
+ hactive = <1366>;
+ hfront-porch = <136>;
+ hback-porch = <60>;
+ hsync-len = <30>;
+ hsync-active = <0>;
+ vactive = <768>;
+ vfront-porch = <8>;
+ vback-porch = <12>;
+ vsync-len = <12>;
+ vsync-active = <0>;
+ };
+
+ ports {
+ panel_in: port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+ };
+};
+
+&edp {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ ports {
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+};
+
+&edp_phy {
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&pinctrl {
+ backlight {
+ bl_pwr_en: bl_pwr_en {
+ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bl_en: bl-en {
+ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_enable_h: lcd-en {
+ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ avdd_1v8_disp_en: avdd-1v8-disp-en {
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
index ff7669eb..2c916c50 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Jerry Rev 3+ board device tree source
*
- * Copyright 2014 Google, Inc
+ * Copyright 2015 Google, Inc
*/
/dts-v1/;
@@ -11,168 +11,454 @@
/ {
model = "Google Jerry";
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+ compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
+ "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
+ "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
+ "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
-
- panel_regulator: panel-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_enable_h>;
- regulator-name = "panel_regulator";
- vin-supply = <&vcc33_sys>;
- };
-
- vcc18_lcd: vcc18-lcd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&avdd_1v8_disp_en>;
- regulator-name = "vcc18_lcd";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc18_wl>;
- };
-
- backlight_regulator: backlight-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_pwr_en>;
- regulator-name = "backlight_regulator";
- vin-supply = <&vcc33_sys>;
- startup-delay-us = <15000>;
- };
-
- sound {
- compatible = "rockchip,audio-max98090-jerry";
-
- cpu {
- sound-dai = <&i2s 0>;
- };
-
- codec {
- sound-dai = <&max98090 0>;
- };
- };
-};
-
-&gpio_keys {
- power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- };
-};
-
-&backlight {
- power-supply = <&backlight_regulator>;
-};
-
-&panel {
- power-supply= <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
regulators {
mic_vcc: LDO_REG2 {
+ regulator-name = "mic_vcc";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "mic_vcc";
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
};
};
+&sdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mwifiex: wifi@1 {
+ compatible = "marvell,sd8897";
+ reg = <1>;
+
+ marvell,caldata-txpwrlimit-2g = /bits/ 8 <
+0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
+0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
+0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
+0x0d 0x09 0x0e 0x09 0x0f 0x09>;
+
+ marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
+0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
+0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
+0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
+0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
+0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
+0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
+0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
+0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
+0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
+0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
+0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
+0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
+0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
+0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
+0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
+0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
+0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
+0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
+0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
+0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
+0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
+0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
+0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
+0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
+0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
+0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
+0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
+0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
+0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
+
+ marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
+0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
+0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
+0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
+0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
+0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
+0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
+0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
+0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
+0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
+0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
+0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
+0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
+0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
+0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
+0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
+0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
+0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
+0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
+0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
+0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
+0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
+0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
+0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
+0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
+0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
+0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
+0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
+0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
+0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
+0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
+0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
+0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
+0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
+0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
+0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
+0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
+0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
+0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
+0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
+0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
+0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
+0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
+0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
+0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
+
+ marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
+0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
+0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
+0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
+0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
+0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
+0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
+0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
+0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
+0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
+0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
+0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
+0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
+0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
+0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
+0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
+0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
+0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
+0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
+0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
+0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
+0x1a 0x05 0x1b 0x05>;
+ };
+};
+
&sdmmc {
+ disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
- disable-wp;
};
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
-&edp {
- pinctrl-names = "default";
- pinctrl-0 = <&edp_hpd>;
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFAULT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "",
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVSOK",
+ "",
+ "EDP_HPD",
+ "DVS1",
+ "nFAULT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
};
&pinctrl {
- backlight {
- bl_pwr_en: bl_pwr_en {
- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
- buck-5v {
- drv_5v: drv-5v {
- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
- edp {
- edp_hpd: edp_hpd {
- rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
- };
- };
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
- emmc {
- /* Make sure eMMC is not in reset */
- emmc_deassert_reset: emmc-deassert-reset {
- rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ buck-5v {
+ drv_5v: drv-5v {
+ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd {
- lcd_enable_h: lcd-en {
- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- avdd_1v8_disp_en: avdd-1v8-disp-en {
- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
@@ -188,24 +474,18 @@
pinctrl-0 = <&i2c4_xfer &trackpad_int>;
trackpad@15 {
- compatible = "elan,i2c_touchpad";
- interrupt-parent = <&gpio7>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
/*
* Remove the inherited pinctrl settings to avoid clashing
* with bus-wide ones.
*/
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
- reg = <0x15>;
- vcc-supply = <&vcc33_io>;
- wakeup-source;
};
trackpad@2c {
compatible = "hid-over-i2c";
interrupt-parent = <&gpio7>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
reg = <0x2c>;
hid-descr-addr = <0x0020>;
vcc-supply = <&vcc33_io>;
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
index 0521d9e0..ffd1121d 100644
--- a/arch/arm/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/dts/rk3288-veyron-mickey.dts
@@ -1,49 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Mickey Rev 0 board device tree source
*
* Copyright 2015 Google, Inc
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
-#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Mickey";
@@ -65,6 +29,13 @@
regulator-boot-on;
vin-supply = <&vcc33_sys>;
};
+
+ sound {
+ compatible = "rockchip,rockchip-audio-max98090";
+ rockchip,model = "VEYRON-HDMI";
+ rockchip,hdmi-codec = <&hdmi>;
+ rockchip,i2s-controller = <&i2s>;
+ };
};
&cpu_thermal {
@@ -112,14 +83,18 @@
cooling-maps {
/*
* After 1st level, throttle the CPU down to as low as 1.4 GHz
- * and don't let the GPU go faster than 400 MHz. Note that we
- * won't throttle the GPU lower than 400 MHz due to CPU
- * heat--we'll let the GPU do the rest itself.
+ * and don't let the GPU go faster than 400 MHz.
*/
cpu_warm_limit_cpu {
trip = <&cpu_alert_warm>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT 4>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
+ <&cpu1 THERMAL_NO_LIMIT 4>,
+ <&cpu2 THERMAL_NO_LIMIT 4>,
+ <&cpu3 THERMAL_NO_LIMIT 4>;
+ };
+ cpu_warm_limit_gpu {
+ trip = <&cpu_alert_warm>;
+ cooling-device = <&gpu 1 1>;
};
/*
@@ -140,29 +115,100 @@
*/
cpu_almost_hot_limit_cpu {
trip = <&cpu_alert_almost_hot>;
- cooling-device =
- <&cpu0 5 6>;
+ cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
+ <&cpu3 5 6>;
};
cpu_hot_limit_cpu {
trip = <&cpu_alert_hot>;
- cooling-device =
- <&cpu0 7 7>;
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
+ <&cpu3 7 7>;
};
cpu_hotter_limit_cpu {
trip = <&cpu_alert_hotter>;
- cooling-device =
- <&cpu0 7 8>;
+ cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
+ <&cpu3 7 8>;
};
cpu_very_hot_limit_cpu {
trip = <&cpu_alert_very_hot>;
- cooling-device =
- <&cpu0 8 THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>,
+ <&cpu1 8 THERMAL_NO_LIMIT>,
+ <&cpu2 8 THERMAL_NO_LIMIT>,
+ <&cpu3 8 THERMAL_NO_LIMIT>;
+ };
+
+ /* At very hot, don't let GPU go over 300 MHz */
+ cpu_very_hot_limit_gpu {
+ trip = <&cpu_alert_very_hot>;
+ cooling-device = <&gpu 2 2>;
};
};
};
-&emmc {
- /delete-property/mmc-hs200-1_8v;
+&gpu_thermal {
+ /delete-node/ trips;
+ /delete-node/ cooling-maps;
+
+ trips {
+ gpu_alert_warmish: gpu_alert_warmish {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_warm: gpu_alert_warm {
+ temperature = <65000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_hotter: gpu_alert_hotter {
+ temperature = <84000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_very_very_hot: gpu_alert_very_very_hot {
+ temperature = <86000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ /* After 1st level throttle the GPU down to as low as 400 MHz */
+ gpu_warmish_limit_gpu {
+ trip = <&gpu_alert_warmish>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT 1>;
+ };
+
+ /*
+ * Slightly after we throttle the GPU, we'll also make sure that
+ * the CPU can't go faster than 1.4 GHz. Note that we won't
+ * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll
+ * let the CPU do the rest itself.
+ */
+ gpu_warm_limit_cpu {
+ trip = <&gpu_alert_warm>;
+ cooling-device = <&cpu0 4 4>,
+ <&cpu1 4 4>,
+ <&cpu2 4 4>,
+ <&cpu3 4 4>;
+ };
+
+ /* When hot, GPU goes down to 300 MHz */
+ gpu_hotter_limit_gpu {
+ trip = <&gpu_alert_hotter>;
+ cooling-device = <&gpu 2 2>;
+ };
+
+ /* When really hot, don't let GPU go _above_ 300 MHz */
+ gpu_very_very_hot_limit_gpu {
+ trip = <&gpu_alert_very_very_hot>;
+ cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
+ };
+ };
};
&i2c2 {
@@ -175,15 +221,13 @@
&i2s {
status = "okay";
- clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
+ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
/delete-property/ vcc6-supply;
/delete-property/ vcc12-supply;
@@ -216,40 +260,183 @@
};
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "",
+ "",
+ "",
+ "PMIC_INT_L",
+ "POWER_BUTTON_L",
+ "",
+ "",
+
+ "",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OT_RESET",
+ "",
+ "",
+ "AP_WARM_RESET_H",
+ "",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "",
+ "nFALUT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "",
+ "EMMC_RST_L";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS_L",
+ "UART0_RTS_L",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "PWM_LOG",
+ "",
+ "",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "",
+
+ "CPU_NMI",
+ "DVSOK",
+ "HDMI_WAKE",
+ "POWER_HDMI_ON",
+ "DVS1",
+ "",
+ "",
+ "DVS2",
+
+ "HDMI_CEC",
+ "",
+ "",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+ >;
+
hdmi {
power_hdmi_on: power-hdmi-on {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
-&sdmmc {
- status = "disabled";
-};
-
-&sdio0 {
- status = "disabled";
-};
-
-&sdmmc {
- status = "disabled";
-};
-
-&spi0 {
- status = "disabled";
-};
-
&usb_host0_ehci {
status = "disabled";
};
@@ -260,7 +447,7 @@
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&power_hdmi_on>;
};
diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts
index b56a3f4f..82fc6fba 100644
--- a/arch/arm/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/dts/rk3288-veyron-minnie.dts
@@ -1,49 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Minnie Rev 0+ board device tree source
*
* Copyright 2015 Google, Inc
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Minnie";
@@ -52,111 +16,31 @@
"google,veyron-minnie-rev0", "google,veyron-minnie",
"google,veyron", "rockchip,rk3288";
- backlight_regulator: backlight-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_pwr_en>;
- regulator-name = "backlight_regulator";
- vin-supply = <&vcc33_sys>;
- startup-delay-us = <15000>;
- };
-
- panel_regulator: panel-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_enable_h>;
- regulator-name = "panel_regulator";
- startup-delay-us = <100000>;
- vin-supply = <&vcc33_sys>;
- };
-
- vcc18_lcd: vcc18-lcd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ volume_buttons: volume-buttons {
+ compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&avdd_1v8_disp_en>;
- regulator-name = "vcc18_lcd";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc18_wl>;
- };
-
- sound {
- compatible = "rockchip,audio-max98090-jerry";
+ pinctrl-0 = <&volum_down_l &volum_up_l>;
- cpu {
- sound-dai = <&i2s 0>;
+ volum_down {
+ label = "Volum_down";
+ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <100>;
};
- codec {
- sound-dai = <&max98090 0>;
+ volum_up {
+ label = "Volum_up";
+ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <100>;
};
};
};
&backlight {
/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
- brightness-levels = <
- 0 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
- power-supply = <&backlight_regulator>;
-};
-
-&emmc {
- /delete-property/mmc-hs200-1_8v;
-};
-
-&gpio_keys {
- pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>;
-
- volum_down {
- label = "Volum_down";
- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <100>;
- };
-
- volum_up {
- label = "Volum_up";
- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <100>;
- };
+ brightness-levels = <3 255>;
+ num-interpolated-steps = <252>;
};
&i2c_tunnel {
@@ -177,18 +61,31 @@
compatible = "elan,ekth3500";
reg = <0x10>;
interrupt-parent = <&gpio2>;
- interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int &touch_rst>;
- reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
vcc33-supply = <&vcc33_touch>;
vccio-supply = <&vcc33_touch>;
};
};
&panel {
- compatible = "auo,b101ean01", "simple-panel";
- power-supply= <&panel_regulator>;
+ compatible = "auo,b101ean01";
+
+ /delete-node/ panel-timing;
+
+ panel-timing {
+ clock-frequency = <66666667>;
+ hactive = <1280>;
+ hfront-porch = <18>;
+ hback-porch = <21>;
+ hsync-len = <32>;
+ vactive = <800>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ vsync-len = <18>;
+ };
};
&rk808 {
@@ -217,86 +114,302 @@
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
&vcc_5v {
enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFALUT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "PROCHOT#",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN",
+ "TOUCH_INT",
+ "TOUCH_RST",
+
+ "I2C3_SCL_TP",
+ "I2C3_SDA_TP";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "dev_wake",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "Volum_Up#",
+ "Volum_Down#",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "",
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVS_OK",
+ "SDMMC_WP",
+ "EDP_HPD",
+ "DVS1",
+ "nFALUT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
- backlight {
- bl_pwr_en: bl_pwr_en {
- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
buck-5v {
drv_5v: drv-5v {
- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
volum_down_l: volum-down-l {
- rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
};
volum_up_l: volum-up-l {
- rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd {
- lcd_enable_h: lcd-en {
- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- avdd_1v8_disp_en: avdd-1v8-disp-en {
- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
prochot {
gpio_prochot: gpio-prochot {
- rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touchscreen {
touch_int: touch-int {
- rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
touch_rst: touch-rst {
- rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/dts/rk3288-veyron-sdmmc.dtsi
new file mode 100644
index 00000000..27fb06ce
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-sdmmc.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron (and derivatives) fragment for sdmmc cards
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+&io_domains {
+ sdcard-supply = <&vccio_sd>;
+};
+
+&pinctrl {
+ sdmmc {
+ /*
+ * We run sdmmc at max speed; bump up drive strength.
+ * We also have external pulls, so disable the internal ones.
+ */
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
+ <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
+ <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
+ <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ /*
+ * Builtin CD line is hooked to ground to prevent JTAG at boot
+ * (and also to get the voltage rail correct).
+ * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
+ * think there's a card inserted
+ */
+ sdmmc_cd_disabled: sdmmc-cd-disabled {
+ rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /* This is where we actually hook up CD */
+ sdmmc_cd_pin: sdmmc-cd-pin {
+ rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&rk808 {
+ vcc9-supply = <&vcc_5v>;
+
+ regulators {
+ vccio_sd: LDO_REG4 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc33_sd: LDO_REG5 {
+ regulator-name = "vcc33_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+};
+
+&sdmmc {
+ status = "okay";
+
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc33_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts
index 58c1fe96..4a3ea934 100644
--- a/arch/arm/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -7,8 +7,8 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
#include "cros-ec-sbs.dtsi"
-#include "rk3288-veyron-speedy-u-boot.dtsi"
/ {
model = "Google Speedy";
@@ -17,44 +17,6 @@
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
-
- panel_regulator: panel-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_enable_h>;
- regulator-name = "panel_regulator";
- startup-delay-us = <100000>;
- vin-supply = <&vcc33_sys>;
- };
-
- vcc18_lcd: vcc18-lcd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&avdd_1v8_disp_en>;
- regulator-name = "vcc18_lcd";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc18_wl>;
- };
-
- backlight_regulator: backlight-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_pwr_en>;
- regulator-name = "backlight_regulator";
- vin-supply = <&vcc33_sys>;
- startup-delay-us = <15000>;
- };
-};
-
-&backlight {
- power-supply = <&backlight_regulator>;
};
&cpu_alert0 {
@@ -65,6 +27,10 @@
temperature = <70000>;
};
+&cpu_crit {
+ temperature = <90000>;
+};
+
&edp {
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
@@ -72,8 +38,12 @@
force-hpd;
};
-&panel {
- power-supply = <&panel_regulator>;
+&gpu_alert0 {
+ temperature = <80000>;
+};
+
+&gpu_crit {
+ temperature = <90000>;
};
&rk808 {
@@ -84,7 +54,7 @@
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
@@ -102,42 +72,253 @@
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFALUT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "PWRLIMIT#_CPU",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "ALS_INT", /* not connected */
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVS_OK",
+ "",
+ "EDP_HOTPLUG",
+ "DVS1",
+ "nFALUT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
- backlight {
- bl_pwr_en: bl_pwr_en {
- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
buck-5v {
drv_5v: drv-5v {
- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd {
- lcd_enable_h: lcd-en {
- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- avdd_1v8_disp_en: avdd-1v8-disp-en {
- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 434b0d49..bd38e6ac 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron (and derivatives) board device tree source
*
- * Copyright 2014 Google, Inc
+ * Copyright 2015 Google, Inc
*/
#include <dt-bindings/clock/rockchip,rk808.h>
@@ -10,150 +10,83 @@
#include "rk3288.dtsi"
/ {
- memory {
- reg = <0x0 0x80000000>;
- };
-
chosen {
- stdout-path = &uart2;
- };
-
- firmware {
- chromeos {
- pinctrl-names = "default";
- pinctrl-0 = <&fw_wp_ap>;
- write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
- };
+ stdout-path = "serial2:115200n8";
};
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 1 2 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
- default-brightness-level = <128>;
- enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
- backlight-boot-off;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en>;
- pwms = <&pwm0 0 1000000 0>;
+ /*
+ * The default coreboot on veyron devices ignores memory@0 nodes
+ * and would instead create another memory node.
+ */
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
};
- panel: panel {
- compatible ="cnm,n116bgeea2","simple-panel";
- status = "okay";
- power-supply = <&vcc33_lcd>;
- backlight = <&backlight>;
- };
- gpio_keys: gpio-keys {
+ power_button: power-button {
compatible = "gpio-keys";
-
pinctrl-names = "default";
- pinctrl-0 = <&pwr_key_h>;
+ pinctrl-0 = <&pwr_key_l>;
+
power {
label = "Power";
- gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
- gpio-key,wakeup;
+ wakeup-source;
};
};
gpio-restart {
compatible = "gpio-restart";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ap_warm_reset_h>;
- priority = /bits/ 8 <200>;
+ priority = <200>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
};
- sound {
- compatible = "rockchip,rockchip-audio-max98090";
- rockchip,model = "ROCKCHIP-I2S";
- rockchip,i2s-controller = <&i2s>;
- rockchip,audio-codec = <&max98090>;
- rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
- rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- rockchip,headset-codec = <&headsetcodec>;
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
pinctrl-names = "default";
- pinctrl-0 = <&mic_det>, <&hp_det>;
- };
-
- vdd_logic: pwm-regulator {
- compatible = "pwm-regulator";
- pwms = <&pwm1 0 2000 0>;
-
- voltage-table = <1350000 0>,
- <1300000 10>,
- <1250000 20>,
- <1200000 31>,
- <1150000 41>,
- <1100000 52>,
- <1050000 62>,
- <1000000 72>,
- < 950000 83>;
+ pinctrl-0 = <&wifi_enable_h>;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_logic";
- regulator-ramp-delay = <4000>;
+ /*
+ * Depending on the actual card populated GPIO4 D4
+ * correspond to one of these signals on the module:
+ *
+ * D4:
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
- vcc33_sys: vcc33-sys {
+ vcc_5v: vcc-5v {
compatible = "regulator-fixed";
- regulator-name = "vcc33_sys";
+ regulator-name = "vcc_5v";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vccsys>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
- vcc_5v: vcc-5v {
+ vcc33_sys: vcc33-sys {
compatible = "regulator-fixed";
- regulator-name = "vcc_5v";
+ regulator-name = "vcc33_sys";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
vcc50_hdmi: vcc50-hdmi {
@@ -164,39 +97,21 @@
vin-supply = <&vcc_5v>;
};
- bt_regulator: bt-regulator {
- /*
- * On the module itself this is one of these (depending
- * on the actual card pouplated):
- * - BT_I2S_WS_BT_RFDISABLE_L
- * - No connect
- */
-
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_l>;
- regulator-name = "bt_regulator";
- };
+ vdd_logic: vdd-logic {
+ compatible = "pwm-regulator";
+ regulator-name = "vdd_logic";
- wifi_regulator: wifi-regulator {
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
+ pwms = <&pwm1 0 1994 0>;
+ pwm-supply = <&vcc33_sys>;
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- regulator-name = "wifi_regulator";
+ pwm-dutycycle-range = <0x7b 0>;
+ pwm-dutycycle-unit = <0x94>;
- /* Faux input supply. See bt_regulator description. */
- vin-supply = <&bt_regulator>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <4000>;
};
};
@@ -204,71 +119,62 @@
cpu0-supply = <&vdd_cpu>;
};
-&efuse {
- status = "okay";
+&cpu_crit {
+ temperature = <100000>;
+};
+
+/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
+&cpu_opp_table {
+ /delete-node/ opp-312000000;
+
+ opp-1512000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp-1608000000 {
+ opp-microvolt = <1300000>;
+ };
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1400000>;
+ };
};
&emmc {
- broken-cd;
+ status = "okay";
+
bus-width = <8>;
cap-mmc-highspeed;
+ rockchip,default-sample-phase = <158>;
+ disable-wp;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
- disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
- status = "okay";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
-&sdio0 {
- broken-cd;
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- cap-sdio-irq;
- card-external-vcc-supply = <&wifi_regulator>;
- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
- <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
- keep-power-in-suspend;
- non-removable;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
+&gpu {
+ mali-supply = <&vdd_gpu>;
status = "okay";
- vmmc-supply = <&vcc33_sys>;
- vqmmc-supply = <&vcc18_wl>;
};
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- card-detect-delay = <200>;
- cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
- num-slots = <1>;
- status = "okay";
- vmmc-supply = <&vcc33_sd>;
- vqmmc-supply = <&vccio_sd>;
+&gpu_alert0 {
+ temperature = <72500>;
};
-&spi2 {
- status = "okay";
+&gpu_crit {
+ temperature = <100000>;
+};
- spi_flash: spiflash@0 {
- compatible = "spidev", "jedec,spi-nor";
- spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
- reg = <0>;
- };
+&hdmi {
+ pinctrl-names = "default", "unwedge";
+ pinctrl-0 = <&hdmi_ddc>;
+ pinctrl-1 = <&hdmi_ddc_unwedge>;
+ status = "okay";
};
&i2c0 {
@@ -280,12 +186,12 @@
rk808: pmic@1b {
compatible = "rockchip,rk808";
+ reg = <0x1b>;
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
- reg = <0x1b>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -297,39 +203,41 @@
vcc6-supply = <&vcc_5v>;
vcc7-supply = <&vcc33_sys>;
vcc8-supply = <&vcc33_sys>;
- vcc9-supply = <&vcc_5v>;
- vcc10-supply = <&vcc33_sys>;
- vcc11-supply = <&vcc_5v>;
vcc12-supply = <&vcc_18>;
-
vddio-supply = <&vcc33_io>;
regulators {
vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1450000>;
- regulator-name = "vdd_arm";
regulator-ramp-delay = <6001>;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
- regulator-name = "vdd_gpu";
regulator-ramp-delay = <6001>;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vcc135_ddr: DCDC_REG3 {
+ regulator-name = "vcc135_ddr";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc135_ddr";
- regulator-suspend-mem-enabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
/*
@@ -340,12 +248,15 @@
* power measurement purposes).
*/
vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
+ regulator-name = "vcc_18";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_18";
- regulator-suspend-mem-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
};
/*
@@ -356,60 +267,47 @@
* (such as danger) they're the same net.
*/
vcc33_io: LDO_REG1 {
+ regulator-name = "vcc33_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_io";
- regulator-suspend-mem-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
};
vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vdd_10";
- regulator-suspend-mem-microvolt = <1000000>;
- };
-
- vccio_sd: LDO_REG4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-suspend-mem-disabled;
- };
-
- vcc33_sd: LDO_REG5 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_sd";
- regulator-suspend-mem-disabled;
- };
-
- vcc18_codec: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_codec";
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
};
vdd10_lcd_pwren_h: LDO_REG7 {
+ regulator-name = "vdd10_lcd_pwren_h";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
- regulator-name = "vdd10_lcd_pwren_h";
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
vcc33_lcd: SWITCH_REG1 {
+ regulator-name = "vcc33_lcd";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc33_lcd";
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
};
};
@@ -436,24 +334,6 @@
clock-frequency = <100000>;
i2c-scl-falling-time-ns = <50>; /* 10ns measured */
i2c-scl-rising-time-ns = <800>; /* 600ns measured */
-
- max98090: max98090@10 {
- compatible = "maxim,max98090";
- reg = <0x10>;
- #sound-dai-cells = <0>;
- interrupt-parent = <&gpio6>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&int_codec>;
- };
-};
-
-&i2c3 {
- status = "okay";
-
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
};
&i2c4 {
@@ -462,55 +342,61 @@
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>; /* 11ns measured */
i2c-scl-rising-time-ns = <300>; /* 225ns measured */
-
- headsetcodec: ts3a227e@3b {
- compatible = "ti,ts3a227e";
- reg = <0x3b>;
- interrupt-parent = <&gpio0>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ts3a227e_int_l>;
- ti,micbias = <7>; /* MICBIAS = 2.8V */
- };
-};
-
-&i2c5 {
- status = "okay";
-
- clock-frequency = <100000>;
- i2c-scl-falling-time-ns = <300>;
- i2c-scl-rising-time-ns = <1000>;
};
-&i2s {
+&io_domains {
status = "okay";
- clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
-};
-&io_domains {
- audio-supply = <&vcc18_codec>;
bb-supply = <&vcc33_io>;
dvp-supply = <&vcc_18>;
flash0-supply = <&vcc18_flashio>;
gpio1830-supply = <&vcc33_io>;
gpio30-supply = <&vcc33_io>;
lcdc-supply = <&vcc33_lcd>;
- sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc18_wl>;
+};
+
+&pwm1 {
status = "okay";
};
-&wdt {
+&sdio0 {
status = "okay";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc33_sys>;
+ vqmmc-supply = <&vcc18_wl>;
};
-&pwm0 {
+&spi2 {
status = "okay";
+
+ rx-sample-delay-ns = <12>;
+
+ spi_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
};
-&pwm1 {
+&tsadc {
status = "okay";
+
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-temp = <125000>;
};
&uart0 {
@@ -519,9 +405,6 @@
/* Pins don't include flow control by default; add that in */
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- /* We need to go faster than 24MHz, so adjust clock parents / rates */
- assigned-clocks = <&cru SCLK_UART0>;
- assigned-clock-rates = <48000000>;
};
&uart1 {
@@ -530,67 +413,47 @@
&uart2 {
status = "okay";
- reg-shift = <2>;
};
-&vopb {
+&usbphy {
status = "okay";
};
-&vopb_mmu {
+&usb_host0_ehci {
status = "okay";
-};
-&vopl {
- status = "okay";
+ needs-reset-on-resume;
};
-&vopl_mmu {
+&usb_host1 {
status = "okay";
+ snps,need-phy-for-wake;
};
-&edp {
+&usb_otg {
status = "okay";
- rockchip,panel = <&panel>;
+
+ assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
+ assigned-clock-parents = <&usbphy0>;
+ dr_mode = "host";
+ snps,need-phy-for-wake;
};
-&hdmi {
+&vopb {
status = "okay";
};
-&gpu {
+&vopb_mmu {
status = "okay";
};
-&tsadc {
- tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
- tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+&wdt {
status = "okay";
};
&pinctrl {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &bt_dev_wake_sleep
- >;
-
- /* Add this for sdmmc pins to SD card */
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ bias-disable;
drive-strength = <8>;
};
@@ -607,33 +470,15 @@
output-low;
};
- backlight {
- bl_en: bl-en {
- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
buttons {
- pwr_key_h: pwr-key-h {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- codec {
- hp_det: hp-det {
- rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- int_codec: int-codec {
- rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- mic_det: mic-det {
- rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
+ pwr_key_l: pwr-key-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
emmc {
emmc_reset: emmc-reset {
- rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
/*
@@ -641,54 +486,59 @@
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
- <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
- };
- };
-
- headset {
- ts3a227e_int_l: ts3a227e-int-l {
- rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
+ <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
};
};
pmic {
pmic_int_l: pmic-int-l {
- /*
- * Causes jerry to hang when probing bus 0
- * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
- */
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
reboot {
ap_warm_reset_h: ap-warm-reset-h {
- rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ recovery-switch {
+ rec_mode_l: rec-mode-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio0 {
wifi_enable_h: wifienable-h {
- rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* NOTE: mislabelled on schematic; should be bt_enable_h */
bt_enable_l: bt-enable-l {
- rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake: bt-host-wake {
+ rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
};
/*
@@ -696,100 +546,48 @@
* We also have external pulls, so disable the internal ones.
*/
sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
+ <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
+ <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
+ <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
};
sdio0_cmd: sdio0-cmd {
- rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
};
sdio0_clk: sdio0-clk {
- rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
};
/*
* These pins are only present on very new veyron boards; on
* older boards bt_dev_wake is simply always high. Note that
- * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
+ * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
* to map this pin everywhere
*/
bt_dev_wake_sleep: bt-dev-wake-sleep {
- rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
};
bt_dev_wake_awake: bt-dev-wake-awake {
- rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
};
- };
- sdmmc {
- /*
- * We run sdmmc at max speed; bump up drive strength.
- * We also have external pulls, so disable the internal ones.
- */
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
- <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- /*
- * Builtin CD line is hooked to ground to prevent JTAG at boot
- * (and also to get the voltage rail correct). Make we
- * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
- * think there's a card inserted
- */
- sdmmc_cd_disabled: sdmmc-cd-disabled {
- rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- /* This is where we actually hook up CD */
- sdmmc_cd_gpio: sdmmc-cd-gpio {
- rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
+ bt_dev_wake: bt-dev-wake {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
tpm {
tpm_int_h: tpm-int-h {
- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
write-protect {
fw_wp_ap: fw-wp-ap {
- rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
-
-&usbphy {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
- needs-reset-on-resume;
-};
-
-&usb_host1 {
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
- assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
- assigned-clock-parents = <&cru SCLK_OTGPHY0>;
-};
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v1 15/15] arm: dts: rockchip: rk3288-evb: fix memory reg value
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (12 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 14/15] arm: dts: rockchip: sync rk3288-veyron DT from Linux Johan Jonker
@ 2022-02-07 3:47 ` Johan Jonker
2022-02-26 18:36 ` [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Simon Glass
14 siblings, 0 replies; 22+ messages in thread
From: Johan Jonker @ 2022-02-07 3:47 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot, w.egorov, hl, jagan, heiko
rk3288.dtsi is updated and changed it's reg size,
so fix memory reg value.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288-evb.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
index 72da8847..7e9a6f45 100644
--- a/arch/arm/dts/rk3288-evb.dtsi
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -6,8 +6,9 @@
#include "rk3288.dtsi"
/ {
- memory {
- reg = <0 0x80000000>;
+ memory@0 {
+ reg = <0x0 0x0 0x0 0x80000000>;
+ device_type = "memory";
};
ext_gmac: external-gmac-clock {
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux
2022-02-07 3:47 [PATCH v1 01/15] rockchip: rk3228-power: sync power domain dt-binding header from Linux Johan Jonker
` (13 preceding siblings ...)
2022-02-07 3:47 ` [PATCH v1 15/15] arm: dts: rockchip: rk3288-evb: fix memory reg value Johan Jonker
@ 2022-02-26 18:36 ` Simon Glass
14 siblings, 0 replies; 22+ messages in thread
From: Simon Glass @ 2022-02-26 18:36 UTC (permalink / raw)
To: Johan Jonker
Cc: Kever Yang, Philipp Tomsich, U-Boot Mailing List, Wadim Egorov,
Lin Huang, Jagan Teki, Heiko Stübner
On Sun, 6 Feb 2022 at 20:47, Johan Jonker <jbx6244@gmail.com> wrote:
>
> In order to update the DT for rk3228
> sync the power domain dt-binding header.
> This is the state as of v5.17 in Linux.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> include/dt-bindings/power/rk3228-power.h | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
> create mode 100644 include/dt-bindings/power/rk3228-power.h
Reviewed-by: Simon Glass <sjg@chromium.org>
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