From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24E0AC433F5 for ; Wed, 9 Feb 2022 00:33:45 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A452C83DAB; Wed, 9 Feb 2022 01:33:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F1D7983D73; Wed, 9 Feb 2022 01:33:41 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id F3C3B83DAB for ; Wed, 9 Feb 2022 01:33:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 40C0F1FB; Tue, 8 Feb 2022 16:33:38 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD7D73F718; Tue, 8 Feb 2022 16:33:37 -0800 (PST) Date: Wed, 9 Feb 2022 00:33:08 +0000 From: Andre Przywara To: Joakim Tjernlund Cc: "u-boot@lists.denx.de" Subject: Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ? Message-ID: <20220209003308.015c087d@slackpad.lan> In-Reply-To: <52270ef295b438af775d6f00e3c6e97f6482d74c.camel@infinera.com> References: <52270ef295b438af775d6f00e3c6e97f6482d74c.camel@infinera.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tue, 8 Feb 2022 22:05:00 +0000 Joakim Tjernlund wrote: Hi Joakim, > Trying to figure out how I should map the MMU for normal RAM so it acessible > from all ELx security states. ^^^^^^^ This does not make much sense. U-Boot is typically running in one exception level only, and sets up the page table for exactly that EL. Each EL uses a separate translation regime (with some twists for stage 2 EL2 and combined EL1/0, plus VHE). If you map your memory in EL3, then drop to EL2, the EL3 page tables become irrelevant. So in U-Boot we just set up the page tables for the EL we are running in, and leave the paging for the lower exception levels to be set up at the discretion of our payloads (kernels, hypervisors). Please not that *secure* memory is a separate concept, and handled by external hardware, typically using regions, not page tables. > So far I have this mem_map: > > /* memory mapped RAM. 32MB */ > .virt = 0x60000000UL, > .phys = 0x60000000UL, > .size = 0x02000000UL, > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE > > but starting to doubt that is correct, can someone suggest what to put in the .attrs field? Those are the correct attributes for normal ("cache-able") memory. However you probably need at least another mapping for MMIO accesses, which MUST NOT be cacheable (MT_DEVICE_NGNRNE), but device memory. See the beginning of arch/arm/mach-sunxi/board.c for an example. Cheers, Andre