From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E35CEC433F5 for ; Wed, 9 Feb 2022 15:41:40 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D0BBF83E9B; Wed, 9 Feb 2022 16:41:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=gin.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5AD3F83E86; Wed, 9 Feb 2022 16:33:36 +0100 (CET) Received: from good-out-27.clustermail.de (good-out-27.clustermail.de [IPv6:2a02:708:0:2c::17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 053D183D3A for ; Wed, 9 Feb 2022 16:33:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=gin.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Daniel.Klauer@gin.de Received: from [10.0.0.3] (helo=frontend.clustermail.de) by smtpout-02.clustermail.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nHoyF-0004Mr-7M for u-boot@lists.denx.de; Wed, 09 Feb 2022 16:33:32 +0100 Received: from [217.6.33.237] (helo=Win2012-02.gin-domain.local) by frontend.clustermail.de with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHoyF-0001o8-5m for u-boot@lists.denx.de; Wed, 09 Feb 2022 16:33:27 +0100 Received: from daniel-desktop2.fritz.box (10.176.8.31) by Win2012-02.gin-domain.local (10.160.128.12) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 9 Feb 2022 16:33:26 +0100 From: Daniel Klauer To: Subject: [PATCH 2/2] net: phy: mv88e6352: Fix miiphy_read/miiphy_write return value checks Date: Wed, 9 Feb 2022 16:32:57 +0100 Message-ID: <20220209153257.284853-2-daniel.klauer@gin.de> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220209153257.284853-1-daniel.klauer@gin.de> References: <20220209153257.284853-1-daniel.klauer@gin.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.176.8.31] X-ClientProxiedBy: Win2012-02.gin-domain.local (10.160.128.12) To Win2012-02.gin-domain.local (10.160.128.12) X-EsetResult: clean, is OK X-EsetId: 37303A29342AAB53617062 X-Mailman-Approved-At: Wed, 09 Feb 2022 16:41:09 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The miiphy_read/miiphy_write functions return 1 on error, not -errno. Fix up the checks accordingly and insert -EIO as fallback error code. Signed-off-by: Daniel Klauer --- drivers/net/phy/mv88e6352.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c index 56060762d8..a87af7ed24 100644 --- a/drivers/net/phy/mv88e6352.c +++ b/drivers/net/phy/mv88e6352.c @@ -36,16 +36,14 @@ static int sw_wait_rdy(const char *devname, u8 phy_addr) { u16 command; u32 timeout = 100; - int ret; /* wait till the SMI is not busy */ do { /* read command register */ - ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); - if (ret < 0) { + if (miiphy_read(devname, phy_addr, COMMAND_REG, &command)) { printf("%s: Error reading command register\n", __func__); - return ret; + return -EIO; } if (timeout-- == 0) { printf("Err..(%s) SMI busy timeout\n", __func__); @@ -69,17 +67,17 @@ static int sw_reg_read(const char *devname, u8 phy_addr, u8 port, command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) | (reg & SMI_MASK); debug("%s: write to command: %#x\n", __func__, command); - ret = miiphy_write(devname, phy_addr, COMMAND_REG, command); - if (ret) - return ret; + if (miiphy_write(devname, phy_addr, COMMAND_REG, command)) + return -EIO; ret = sw_wait_rdy(devname, phy_addr); if (ret) return ret; - ret = miiphy_read(devname, phy_addr, DATA_REG, data); + if (miiphy_read(devname, phy_addr, DATA_REG, data)) + return -EIO; - return ret; + return 0; } static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, @@ -93,16 +91,14 @@ static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, return ret; debug("%s: write to data: %#x\n", __func__, data); - ret = miiphy_write(devname, phy_addr, DATA_REG, data); - if (ret) - return ret; + if (miiphy_write(devname, phy_addr, DATA_REG, data)) + return -EIO; value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) | (reg & SMI_MASK); debug("%s: write to command: %#x\n", __func__, value); - ret = miiphy_write(devname, phy_addr, COMMAND_REG, value); - if (ret) - return ret; + if (miiphy_write(devname, phy_addr, COMMAND_REG, value)) + return -EIO; ret = sw_wait_rdy(devname, phy_addr); if (ret) -- 2.32.0