From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9B86C433F5 for ; Mon, 14 Feb 2022 23:29:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 32BF1839FB; Tue, 15 Feb 2022 00:29:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="tHbe5sQc"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 560FD83879; Tue, 15 Feb 2022 00:29:11 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 044138391E for ; Tue, 15 Feb 2022 00:28:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id AB177B8172F; Mon, 14 Feb 2022 23:28:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F6E0C340EB; Mon, 14 Feb 2022 23:28:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644881330; bh=uR1QLaALDkNyDd4uZD+8Jmq8k7wXFBZxW2XhbCcMJ4U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tHbe5sQcXuezqMpCiyNTUy2wuZE/TypKtUtLQSstZxYl0+1B8opxE4UXqWE/HA1KJ JBbq/gODGehz1isfxtDEK507PI/SLz8kU9DKPYg4Q8Fd4K1a9OXQjuEbOuk5/g5gGy 9lIczpETgl1+M4U9/YiEzFnJlfPCTlcm5Xhxcpg1nS8Gd0poB41/i3bqJc3VAWlZvx 0KTHIsjsRwzdcZMypOZMbb5tRvYjd9Zvm7vAvFz3lZ/sJPdcOxRUoSo85KqSrorYOT rhEJ0+kBcoZQmMuuxyvRt0ODIM+FZcMJTOPa850Jsyxg/1Xg/FhEPtCbp1K86qZ5+D MjYkQiCuqeA2g== Received: by pali.im (Postfix) id 0BC8120A3; Tue, 15 Feb 2022 00:28:48 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-mvebu 2/3] arm: mvebu: a37xx: Map CCI-400 and AP BootROM address space Date: Tue, 15 Feb 2022 00:28:34 +0100 Message-Id: <20220214232835.12924-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220214232835.12924-1-pali@kernel.org> References: <20220214232835.12924-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean In function build_mem_map() prepares also mapping for CCI-400 and AP BootROM address space. A53 AP BootROM by default starts at address 0xfff00000 and is 16 kB long. CCI-400 in new TF-A version starts at address 0xfe000000 and is 64 kB long. Physical addresses are read directly from mvebu registers, so if TF-A remaps it in future then it would not cause any issue. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/armada3700/cpu.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 9da0d08f947c..e01fea130022 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -40,8 +40,10 @@ #define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc) #define MVEBU_CPU_DEC_WIN_GRANULARITY 16 #define MVEBU_CPU_DEC_WINS 5 +#define MVEBU_CPU_DEC_CCI_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0) +#define MVEBU_CPU_DEC_ROM_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4) -#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2) +#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 4) #define A3700_PTE_BLOCK_NORMAL \ (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE) @@ -104,8 +106,26 @@ static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size) static void build_mem_map(void) { int win, region; + u32 reg; region = 1; + + /* CCI-400 */ + reg = readl(MVEBU_CPU_DEC_CCI_BASE); + mvebu_mem_map[region].phys = reg << 20; + mvebu_mem_map[region].virt = reg << 20; + mvebu_mem_map[region].size = 0x10000; + mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE; + ++region; + + /* AP BootROM */ + reg = readl(MVEBU_CPU_DEC_ROM_BASE); + mvebu_mem_map[region].phys = reg << 20; + mvebu_mem_map[region].virt = reg << 20; + mvebu_mem_map[region].size = 0x4000; + mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL; + ++region; + for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) { u32 base, tgt, size; u64 attrs; -- 2.20.1