From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7999BC4321E for ; Tue, 15 Feb 2022 10:24:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B7C2781DB4; Tue, 15 Feb 2022 11:24:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="gXMRs1sI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1ABC783801; Tue, 15 Feb 2022 11:24:06 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9075081DB4 for ; Tue, 15 Feb 2022 11:24:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E1D14B817F6; Tue, 15 Feb 2022 10:24:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A09FC340EB; Tue, 15 Feb 2022 10:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644920639; bh=9f133IEolL+UaH2KxkzekHorDpgjKjItZBmcsnPppVU=; h=From:To:Cc:Subject:Date:From; b=gXMRs1sIJ03PaqjhcRiFjug9VEyjC7Do+Qmg818MDp2h/wdJtcK2KGP4fQC6IgZOg 29Fs0xYj21BPFFgMV9Frojm+sw4R13F34VG2IHXqASpDZEGrRby9JCs5itPQtShyLZ lyZk2Eh8Ri0KkGWUvriiNxTL4WZbkL4rmwB95wFzYF8t1OqS4sbfxfvJ5jsCLH8/Ug RFsbt7BgrP3fDJaRYDBuvKVrh1Zv45ceG4+LrMsQlEDt1n/dWWLgmwjm/dpxPF4+zl exUWUQdGL+/tlTryDwU4C7f5d1YYksN5iRGVcRDZXHKhhV0eNcEzMC77pbJEKL+pLf IW7bz374/8P9w== Received: by pali.im (Postfix) id 167D3F13; Tue, 15 Feb 2022 11:23:57 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 1/3] arm: a37xx: pci: Do not try to access other buses when link is down Date: Tue, 15 Feb 2022 11:23:35 +0100 Message-Id: <20220215102337.18426-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean If a PIO request is executed while link-down, the whole controller gets stuck in a non-functional state, and even after link comes up again, PIO requests won't work anymore, and a reset of the whole PCIe controller is needed. Therefore we need to prevent sending PIO requests while the link is down. Signed-off-by: Pali Rohár --- drivers/pci/pci-aardvark.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 1eb257ea8b4a..ccaeecaca8e3 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -177,6 +177,23 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg) return readl(pcie->base + reg); } +/** + * pcie_advk_link_up() - Check if PCIe link is up or not + * + * @pcie: The PCI device to access + * + * Return true on link up. + * Return false on link down. + */ +static bool pcie_advk_link_up(struct pcie_advk *pcie) +{ + u32 val, ltssm_state; + + val = advk_readl(pcie, ADVK_LMI_PHY_CFG0); + ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT; + return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED; +} + /** * pcie_advk_addr_valid() - Check for valid bus address * @@ -195,6 +212,10 @@ static bool pcie_advk_addr_valid(struct pcie_advk *pcie, if (busno == 0 && (dev != 0 || func != 0)) return false; + /* Access to other buses is possible when link is up */ + if (busno != 0 && !pcie_advk_link_up(pcie)) + return false; + /* * In PCI-E only a single device (0) can exist on the secondary bus. * Beyond the secondary bus, there might be a Switch and anything is @@ -618,23 +639,6 @@ retry: return ret; } -/** - * pcie_advk_link_up() - Check if PCIe link is up or not - * - * @pcie: The PCI device to access - * - * Return 1 (true) on link up. - * Return 0 (false) on link down. - */ -static int pcie_advk_link_up(struct pcie_advk *pcie) -{ - u32 val, ltssm_state; - - val = advk_readl(pcie, ADVK_LMI_PHY_CFG0); - ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT; - return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED; -} - /** * pcie_advk_wait_for_link() - Wait for link training to be accomplished * -- 2.20.1