From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15D32C433F5 for ; Tue, 15 Feb 2022 19:03:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 111B582F5E; Tue, 15 Feb 2022 20:02:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="d2zXR4AJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 92EF98005D; Tue, 15 Feb 2022 20:02:56 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BBB8882DB7 for ; Tue, 15 Feb 2022 20:02:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A619261741; Tue, 15 Feb 2022 19:02:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9774C340EB; Tue, 15 Feb 2022 19:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644951772; bh=1LcrskcHDse3lHCbdngepuAFT5Yy3B4XXxdsx/0zXJk=; h=From:To:Cc:Subject:Date:From; b=d2zXR4AJsrGwPq4Mlel+JfcTd+zGQhHmCwgnnZTkTC7bIws/ixPjw+DQQM8HA2nTQ PfjAWlUyQv6SrzhF21l2LoR2JN9uxfxynnHpo0iTQk99EqJCPT4Zvbs4CypoWiH9LM SKeiJWpp/RsXhI7WwRUbPzuNTsqAs9FLK9Wo+TBTGWl+sOL0mHoElN2mqKsTwLiT0j ZBothp7gQ0I9/87VyStlfdC/7Q7OKEponbC4TdVuGgmfhgzF4OeC/Zds4WaRpXZBzs 2M3jpENWHJ2VTqUr90PbRr2xuEEk34WPOs3L0ZLyp+vtFUN/m7ide0xORIk32O0sgK jmdj0oM5fmOyA== Received: by pali.im (Postfix) id B68CCF13; Tue, 15 Feb 2022 20:02:49 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andre Przywara , Chia-Wei Wang Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell] arm: mvebu: Do not define or overwrite vectors in SPL build Date: Tue, 15 Feb 2022 20:02:33 +0100 Message-Id: <20220215190233.16248-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean U-Boot SPL is executed by the BootROM. And BootROM expects that U-Boot SPL code returns back to the BootROM. Reset vectors during execution of U-Boot SPL should not be changed as BootROM does not expect it and uses its own reset vectors. Add ifdefs which disable overwriting reset vectors for 32-bit mvebu platforms on which U-Boot SPL should returns back to the BootROM. Signed-off-by: Pali Rohár --- arch/arm/cpu/armv7/start.S | 7 ++++--- arch/arm/lib/vectors.S | 6 ++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index af87a5432ae5..b8175ea3808b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -99,10 +99,11 @@ switch_to_hypervisor_ret: /* * Setup vector: - * (OMAP4 spl TEXT_BASE is not 32 byte aligned. - * Continue to use ROM code vector only in OMAP4 spl) + * OMAP4 spl TEXT_BASE is not 32 byte aligned. + * 32-bit mvebu spl returns execution back to BootROM and should not change vectors. + * Continue to use ROM code vector only in OMAP4 or 32-bit mvebu spl. */ -#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) +#if !((defined(CONFIG_OMAP44XX) || (defined(CONFIG_ARCH_MVEBU) && defined(CONFIG_ARMADA_32BIT))) && defined(CONFIG_SPL_BUILD)) /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 56f36815582b..a0646e213b6d 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -24,6 +24,7 @@ #else b reset #endif +#if !(defined(CONFIG_ARCH_MVEBU) && defined(CONFIG_ARMADA_32BIT) && defined(CONFIG_SPL_BUILD)) ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -31,6 +32,7 @@ ldr pc, _not_used ldr pc, _irq ldr pc, _fiq +#endif .endm @@ -87,6 +89,7 @@ _start: ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ +#if !(defined(CONFIG_ARCH_MVEBU) && defined(CONFIG_ARMADA_32BIT) && defined(CONFIG_SPL_BUILD)) /* ************************************************************************* * @@ -118,6 +121,7 @@ _irq: .word irq _fiq: .word fiq .balignl 16,0xdeadbeef +#endif /* ************************************************************************* @@ -131,6 +135,7 @@ _fiq: .word fiq #ifdef CONFIG_SPL_BUILD +#if !(defined(CONFIG_ARCH_MVEBU) && defined(CONFIG_ARMADA_32BIT) && defined(CONFIG_SPL_BUILD)) .align 5 undefined_instruction: software_interrupt: @@ -141,6 +146,7 @@ irq: fiq: 1: b 1b /* hang and never return */ +#endif #else /* !CONFIG_SPL_BUILD */ -- 2.20.1