From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A8F5C433EF for ; Thu, 17 Feb 2022 09:28:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 798CD83B6E; Thu, 17 Feb 2022 10:27:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Es7V8iM4"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0A83A83A6A; Thu, 17 Feb 2022 10:27:24 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 799F283B67 for ; Thu, 17 Feb 2022 10:27:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CB5D661CDE; Thu, 17 Feb 2022 09:26:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E7B5C340EB; Thu, 17 Feb 2022 09:26:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645090019; bh=JusFE1Rjk9Fu/dPznT1XktmhujEzTodJpMlCYgP0aXM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Es7V8iM4wCaq0KMPB3Jwq8oLOz1GrgYUkQTn8Q6Z0W+Sy1pSBR1qVzjUd2CgH92Z6 8XqZS6ggWSpOiaw+DTwyBSNdN3Os5rRLyNMisoeu7wxP5VhgrfeHNQ6Y7W8SxIYbe7 KYDpMleVhEiBJC1JGzHLOPfim7V86ExKTq7rTR6+pzeHHFkXp0dT19x3CCglOBLDQx 0c0sM/hQl5CWr5mtnSBqVdG/FMyiJN043AdTXMMaA+NqLaez5hCfMh7cvfQjs6QICL 394uEus3kO8wCKvlzl+HS7W0sm3QX9+eRANmzf4U0mEK7UiIIAYUtzcK9dl0w70/xg NeZbecmeTAFhg== Received: by pali.im (Postfix) id 395081187; Thu, 17 Feb 2022 10:26:59 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Konstantin Porotchkin , Vladimir Vid Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-mvebu 5/5] arm: mvebu: a37xx: Add support for reading Security OTP values Date: Thu, 17 Feb 2022 10:26:19 +0100 Message-Id: <20220217092619.1445-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220217092619.1445-1-pali@kernel.org> References: <20220217092619.1445-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Only secure CM3 core can access Security OTP. It is not possible via A53 core on which is running U-Boot. Marvell for this purpose defined mbox API for sending OTP commands between CM and A53 cores. Implement this Marvell mbox API via U-Boot fuse API. Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2). Write support is not implemented yet. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/armada3700/efuse.c | 40 ++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 03778f17ea49..274d9c72c073 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) @@ -77,6 +78,42 @@ static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) } } +static int rwtm_otp_read(u8 row, u32 word, u32 *data) +{ + u32 out[3]; + u32 in[2]; + int res; + + /* + * MBOX_CMD_OTP_READ_32B command is supported by Marvell fuse.bin + * firmware and also by new (yet unreleased) CZ.NIC wtmi firmware. + * But this command does not provide access to lock bit. + */ + if (word < 2) { + in[0] = row; + in[1] = word * 32; + res = mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 2); + if (res != -ENOSYS) { + if (!res) + *data = out[0]; + return res; + } + /* Fallback for old version of CZ.NIC wtmi firmware. */ + } + + /* + * MBOX_CMD_OTP_READ command is supported only by CZ.NIC wtmi firmware + * (in all versions) and provide access to all bits, including lock bit. + * Note that CZ.NIC wtmi firmware may be compiled to disallow access to + * OTP (for security reasons), so this command may fail too. + */ + in[0] = row; + res = mbox_do_cmd(MBOX_CMD_OTP_READ, in, 1, out, 3); + if (!res) + *data = out[word]; + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -96,8 +133,7 @@ int fuse_read(u32 bank, u32 word, u32 *val) if (bank <= RWTM_MAX_BANK) { if (word >= RWTM_ROW_WORDS) return -EINVAL; - /* TODO: not implemented yet */ - return -ENOSYS; + return rwtm_otp_read(bank, word, val); } else if (bank == OTP_NB_BANK) { u32 data[OTP_NB_WORDS]; if (word >= OTP_NB_WORDS) -- 2.20.1