From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11C19C433EF for ; Thu, 17 Feb 2022 20:54:58 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EE57A83A81; Thu, 17 Feb 2022 21:54:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=permerror header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="YR1q9kyh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 423CA83B85; Thu, 17 Feb 2022 21:54:54 +0100 (CET) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EDD2583A81 for ; Thu, 17 Feb 2022 21:54:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=permerror header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marek.behun@nic.cz Received: from thinkpad (unknown [172.20.6.87]) by mail.nic.cz (Postfix) with ESMTPSA id 485E913FDB0; Thu, 17 Feb 2022 21:54:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1645131290; bh=SfR7XAYEt8duJsbwvISc5ep7C1MMkng5OqFBCkhKv1c=; h=Date:From:To; b=YR1q9kyht/REKeybZfCZzNvPA5tLAhaV8C5HhwzhF8AuJaTG/AV6ZDduzseyvuI4g 2Ye+w5qFPWlpu1THGlO8MNkxLVRbtBRtVTGgRkonLiFPTEEhy45KO16VjzDHE88w+B DSlGKC7zozhG83QuPEg8u/EimRrF7uGS9jaCpx5E= Date: Thu, 17 Feb 2022 21:54:49 +0100 From: Marek =?UTF-8?B?QmVow7pu?= To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Stefan Roese , Konstantin Porotchkin , Vladimir Vid , u-boot@lists.denx.de Subject: Re: [PATCH u-boot-mvebu v2 5/5] arm: mvebu: a37xx: Add support for reading Security OTP values Message-ID: <20220217215449.57febf88@thinkpad> In-Reply-To: <20220217185046.2349-6-pali@kernel.org> References: <20220217092619.1445-1-pali@kernel.org> <20220217185046.2349-1-pali@kernel.org> <20220217185046.2349-6-pali@kernel.org> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Feb 2022 19:50:46 +0100 Pali Roh=C3=A1r wrote: > It is not possible for the A53 core (on which U-Boot is running) to read = it > directly. For this purpose Marvell defined mbox API for sending OTP > commands between CM3 and A53 cores. >=20 > Implement these Marvell fuse reading mbox commands via U-Boot fuse API. >=20 > Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via = 44 > banks and words 0-2). >=20 > Note that of the 67 bits, the 3 upper bits are: 1 lock bit and 2 > auxiliary bits (meant for testing during the manufacture of the SOC, as > I understand it). >=20 > Also note that the lock bit and the auxiliary bits are not readable > via Marvell commands. >=20 > With CZ.NIC's commands the lock bit is readable. >=20 > Write support is not implemented yet. >=20 > Signed-off-by: Pali Roh=C3=A1r > --- > arch/arm/mach-mvebu/armada3700/efuse.c | 38 ++++++++++++++++++++++++-- > 1 file changed, 36 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu= /armada3700/efuse.c > index 03778f17ea49..fcf6edd08ce1 100644 > --- a/arch/arm/mach-mvebu/armada3700/efuse.c > +++ b/arch/arm/mach-mvebu/armada3700/efuse.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > =20 > #define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) > @@ -77,6 +78,40 @@ static void otp_read_parallel(void __iomem *base, u32 = *data, u32 count) > } > } > =20 > +static int rwtm_otp_read(u8 row, u32 word, u32 *data) > +{ > + u32 out[3]; > + u32 in[2]; > + int res =3D -EINVAL; > + > + if (word < 2) { > + /* > + * MBOX_CMD_OTP_READ_32B command is supported by Marvell > + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. > + * This command returns raw bits without ECC corrections. > + * It does not provide access to the lock bit. > + */ > + in[0] =3D row; > + in[1] =3D word * 32; > + res =3D mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 2); > + if (!res) > + *data =3D out[0]; > + } else if (word =3D=3D 2) { > + /* > + * MBOX_CMD_OTP_READ command is supported only by CZ.NIC wtmi > + * firmware and provide nitpick: *provides Reviewed-by: Marek Beh=C3=BAn