From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 206DFC433EF for ; Mon, 21 Feb 2022 20:56:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DBD4183C34; Mon, 21 Feb 2022 21:56:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1645476980; bh=qln+qX2eanajCnLLf12Yl41LHbIEELCiZp5p117hqAc=; h=From:To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=lOzvOhki8QfhUpmvdiELIuCLZVAOw9a49fEfcRdCh0bcjplyUnQsrZEPg1NtHCg1m rhCP81OwYHFIGeN929m0KnEpmDg+Fserm8wQVTXhjcQhEGwNJTh26MkrsErvwN120n QEtVYL5M4WuxMAluOGX6wte17o5H8uBi2IiZWRiOOFLzArc1+uUnPMhWULFyenzev2 avz7cvK710ntUsX0IJiNvS2AfzopeZhZR7URZo4JBXLk4galQVh/HPk1NvqEjbXrDH nyI/2BRYbe3XtMm5JhEhYqiBIrsgSPkeo25s6XkF9A+8g4ixZ7o5I93e0jf/scrB5Z f/l34uaqcM9Ig== Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 7E9E283A34; Mon, 21 Feb 2022 21:56:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1645476977; bh=qln+qX2eanajCnLLf12Yl41LHbIEELCiZp5p117hqAc=; h=From:To:Cc:Subject:Date:From; b=qicBSuL/fC/cU8tHSFzNatGgba7uyA5gQtFdoxI/8uS0ewEC7vJcbPKxwpzhBQ+WR HVIi0XA5oFe8m27owjxFfv9R3xAlyAgmqYktpWJqRyFhiGgvIasATcInDpHWvC49nh AIRyEzkQl6i15ULF+aUIVDfn37TxAZaPIPz+9pau8rUlfDLtXK8leieE2JpwF6YG1A sKAbZeNSscuCGvxmpOwq3svfNF3/gfgGHIs3zFOCf8xpnBymTSUuBir4cfoLRjIZLq Hm6y17MSGbA1gyfG6F5S4Lo8J+kov17DOoKlPMuVslCA8exn7T7p+EIYOKYpJ2nsaW Tf6VXEkFCqSCQ== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Patrick Delaunay , Patrice Chotard Subject: [PATCH v2 1/2] ram: stm32mp1: Unconditionally enable ASR Date: Mon, 21 Feb 2022 21:55:59 +0100 Message-Id: <20220221205600.166142-1-marex@denx.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW). Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard --- V2: Rebase on latest changes in this driver past v2022.01 --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 25 ++++++++++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 6 ++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 4d78aa5cb13..04fc8eab909 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -27,6 +27,8 @@ #define RCC_DDRITFCR_DPHYAPBRST (BIT(17)) #define RCC_DDRITFCR_DPHYRST (BIT(18)) #define RCC_DDRITFCR_DPHYCTLRST (BIT(19)) +#define RCC_DDRITFCR_DDRCKMOD_MASK (0x7 << 20) +#define RCC_DDRITFCR_DDRCKMOD_ASR (0x1 << 20) struct reg_desc { const char *name; @@ -651,6 +653,26 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } +static void stm32mp1_asr_enable(struct ddr_info *priv) +{ + struct stm32mp1_ddrctl *ctl = priv->ctl; + + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_ASR); + + start_sw_done(ctl); + + setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN); + writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | + DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), + &ctl->pwrtmg); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + /* board-specific DDR power initializations. */ __weak int board_ddr_power_init(enum ddr_type ddr_type) { @@ -822,6 +844,9 @@ start: stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); +/* Enable auto-self-refresh, which saves a bit of power at runtime. */ + stm32mp1_asr_enable(priv); + /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index f1a26e31f6c..42be1ba57c7 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -265,8 +265,14 @@ struct stm32mp1_ddrphy { #define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n) (((n) & 0xff) << 16) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n) ((n) & 0x1f) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) -- 2.34.1