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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:39 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 08/11] rockchip: rk3568: enable automatic clock gating Date: Mon, 21 Feb 2022 20:31:27 -0500 Message-Id: <20220222013131.3114990-9-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable automatic clock gating on rk3568, which solves a 7c temperature difference on SoQuartz compared to downstream. Signed-off-by: Peter Geis --- arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 5f239d89a7a9..0e0a7f5b54f2 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -25,6 +25,15 @@ #define EMMC_HPROT_SECURE_CTRL 0x03 #define SDMMC0_HPROT_SECURE_CTRL 0x01 +#define PMU_BASE_ADDR 0xfdd90000 +#define PMU_NOC_AUTO_CON0 (0x70) +#define PMU_NOC_AUTO_CON1 (0x74) +#define EDP_PHY_GRF_BASE 0xfdcb0000 +#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) +#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) +#define CPU_GRF_BASE 0xfdc30000 +#define GRF_CORE_PVTPLL_CON0 (0x10) + /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -99,6 +108,20 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD + /* + * When perform idle operation, corresponding clock can + * be opened or gated automatically. + */ + writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); + writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); + + /* Disable eDP phy by default */ + writel(0x00070007, EDP_PHY_GRF_CON10); + writel(0x0ff10ff1, EDP_PHY_GRF_CON0); + + /* Set core pvtpll ring length */ + writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); + /* Set the emmc sdmmc0 to secure */ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 | SDMMC0_HPROT_SECURE_CTRL << 4)); -- 2.25.1