From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9362EC433EF for ; Wed, 23 Feb 2022 13:22:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 44A2783BC6; Wed, 23 Feb 2022 14:22:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Fku/MJ1g"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0888B83C97; Wed, 23 Feb 2022 14:22:24 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CBEFE83B73 for ; Wed, 23 Feb 2022 14:22:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BC306614E7; Wed, 23 Feb 2022 13:22:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C425C340E7; Wed, 23 Feb 2022 13:22:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645622539; bh=pSYv4fy5XQzkSP+Kl9HRpeWYK+nKrOS+xYut3BnrMuY=; h=From:To:Cc:Subject:Date:From; b=Fku/MJ1gV/ekj3UoWo59mrjpDwJdWq5g2YNAXJ1qzxXfVmGL8ENtO/3bzHD4qObu7 4kYPTc1ygUhD3lDUelPBXgczWo8rwsHlTQbNB0KPXPnJ8IeepAWbxA1zPhOB6ygTc5 HxOrxxuYIh3FXePBg2kV3FN17ViPL21CJv+31oiqMihEzvdF//+pDA05LwVJgmZt7R eAjwEY7qtJYjx/mu/ssSYKo7maZLO+ZoPzbeSWLv/PFpgJtF8ofTqP8MheLVjNiUUd 2H1wlJD2P5MDpM/6FgFoXyLnqujdOiIqKhI3yGGIy5poAT5u2hJpi6b7SgRTLvuzqS kkpH9/FuWcemA== Received: by pali.im (Postfix) id 7147E89B; Wed, 23 Feb 2022 14:22:16 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-mvebu] watchdog: armada_37xx: Probe driver also when watchdog is already running Date: Wed, 23 Feb 2022 14:21:40 +0100 Message-Id: <20220223132140.12529-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean If Armada 37xx watchdog is started before U-Boot then CNTR_CTRL_ACTIVE bit is set, U-Boot armada-37xx-wdt.c driver fails to initialize and so U-Boot is unable to use or kick this watchdog. Do not check for CNTR_CTRL_ACTIVE bit and always initialize watchdog. Same behavior is implemented in Linux kernel driver. This change allows to activate watchdog in firmware which loads U-Boot. Signed-off-by: Pali Rohár --- drivers/watchdog/armada-37xx-wdt.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 2e119b9b5aad..bacebbc7926a 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -58,13 +58,11 @@ static void counter_disable(struct a37xx_wdt *priv, int id) clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); } -static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src) +static void init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src) { u32 reg; reg = readl(priv->reg + CNTR_CTRL(id)); - if (reg & CNTR_CTRL_ACTIVE) - return -EBUSY; reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK | CNTR_CTRL_TRIG_SRC_MASK); @@ -79,8 +77,6 @@ static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src) reg |= trig_src; writel(reg, priv->reg + CNTR_CTRL(id)); - - return 0; } static int a37xx_wdt_reset(struct udevice *dev) @@ -116,16 +112,9 @@ static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags) static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags) { struct a37xx_wdt *priv = dev_get_priv(dev); - int err; - - err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0); - if (err < 0) - return err; - err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, - CNTR_CTRL_TRIG_SRC_PREV_CNTR); - if (err < 0) - return err; + init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0); + init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, CNTR_CTRL_TRIG_SRC_PREV_CNTR); priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; -- 2.20.1