From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Fabio Estevam <festevam@denx.de>,
Peng Fan <peng.fan@nxp.com>, Stefano Babic <sbabic@denx.de>
Subject: [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode
Date: Sat, 26 Feb 2022 04:37:42 +0100 [thread overview]
Message-ID: <20220226033742.95540-2-marex@denx.de> (raw)
In-Reply-To: <20220226033742.95540-1-marex@denx.de>
Add entry for 3732 MT/s mode of operation of the LPDDR4, in
which case the DDR PLL has to be configured in 933 MHz mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index 0f8baefb1f8..a54449e5f14 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3732:
+ dram_pll_init(MHZ(933));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
--
2.34.1
next prev parent reply other threads:[~2022-02-26 3:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
2022-02-26 3:37 ` Marek Vasut [this message]
2022-02-26 12:56 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Fabio Estevam
2022-04-12 18:47 ` sbabic
2022-02-26 12:55 ` [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Fabio Estevam
2022-03-21 2:48 ` Peng Fan (OSS)
2022-03-21 3:03 ` Marek Vasut
2022-04-12 18:42 ` sbabic
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