From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 593E5C433F5 for ; Wed, 2 Mar 2022 11:51:29 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A9DCC83C9B; Wed, 2 Mar 2022 12:50:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="iErPa/7y"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DBC0E83CBB; Wed, 2 Mar 2022 12:50:10 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 120D183CA8 for ; Wed, 2 Mar 2022 12:49:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B6799B81FA2; Wed, 2 Mar 2022 11:49:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F382C004E1; Wed, 2 Mar 2022 11:49:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1646221778; bh=5PPF2/zzPIsLwVajRzy5LT9+ZtSSFHsF1CqpQ/1QM04=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iErPa/7yaVPX1l0gSBRv4G3RgRTG/p95hVZsu2bUyEcKGu7HBLoN1fE9VKMvllp9o 1sPklieRbVsd3X9Can1D69fXVsgM26B2xAlYyyHW0McuvdxGZyEWw1tdu3JBGzd0H1 F0a7Kr4fmQGpLDwSe2wyl2oXGdTMhD0xrq3NLjuo0os2TLqkB6RN7YpkC2xSJbU29z Bu8Ixz/66pM59nKMEzvak1dkujaiVimwF+/jlN5fr7R6W4jnqs3Z8PQD8MWSdfOVY1 J48xnQUJfsF1Md6mkbL4SMpimIuGEN5h3ZhRy7MwDvKSOMt6mgrt1bevMFlOGAiF1o 6ogtDGEPYgzxg== Received: by pali.im (Postfix) id DEC9D677; Wed, 2 Mar 2022 12:49:37 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 8/8] arm: mvebu: turris_omnia: Add support for USB3.0 mode in WWAN MiniPCIe slot Date: Wed, 2 Mar 2022 12:47:58 +0100 Message-Id: <20220302114758.21787-9-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220302114758.21787-1-pali@kernel.org> References: <20220302114758.21787-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean PCIe Mini CEM 2.1 spec added support for USB3.0 mode on MiniPCIe cards. USB3.0 and PCIe share same pins and only one function can be active at the same time. PCIe Mini CEM 2.1 spec says that determining function is platform specific and spec does not define any dedicated pin which could say if card is USB3.0-based or PCIe-based. Implement this platform specific decision (USB3.0 vs PCIe) for WWAN MiniPCIe slot on Turris Omnia via U-Boot env variable "omnia_wwan_slot", similarly like is implemented forced mode for MiniPCIe/mSATA slot via "omnia_msata_slot" env variable. Value "usb3" for "omnia_wwan_slot" would mean to set USB3.0 mode and value "pcie" original PCIe mode. A385 SoC on Turris Omnia has configurable fifth SerDes line (exported to MiniPCIe WWAN slot with SIM card) either to USB3.0 or PCIe functionality, so implementation of this new PCIe Mini CEM 2.1 feature is simple, by just configuring SerDes to USB 3.0 mode. Other twos MiniPCIe slots on Turris Omnia do not have this new functionality as their SerDes lines cannot be switched to USB3.0 functionality. Note that A385 SoC does not have too many USB3.0 blocks, so activating USB3.0 in MiniPCIe cause that one external USB3.0 USB-A port would loose USB3.0 functionality and would be downgraded just to USB2.0. By default this MiniPCIe WWAN slot is in PCIe mode, like before. To set this MiniPCIe WWAN slot to USB3.0 mode, call U-Boot commands: => setenv omnia_wwan_slot usb3 => saveenv => reset Signed-off-by: Pali Rohár --- board/CZ.NIC/turris_omnia/turris_omnia.c | 57 ++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index e2f4daa827ed..83cfc80d1930 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -246,6 +246,22 @@ static bool omnia_detect_sata(const char *msata_slot) return stsword & MSATA_IND_STSBIT ? true : false; } +static bool omnia_detect_wwan_usb3(const char *wwan_slot) +{ + puts("WWAN slot configuration... "); + + if (wwan_slot && strcmp(wwan_slot, "usb3") == 0) { + puts("USB3.0\n"); + return true; + } + + if (wwan_slot && strcmp(wwan_slot, "pcie") != 0) + printf("unsupported env value '%s', fallback to... ", wwan_slot); + + puts("PCIe+USB2.0\n"); + return false; +} + void *env_sf_get_env_addr(void) { /* SPI Flash is mapped to address 0xD4000000 only in SPL */ @@ -276,6 +292,20 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) board_serdes_map[0].serdes_mode = SERDES_DEFAULT_MODE; } +#ifdef CONFIG_SPL_ENV_SUPPORT + /* beware that env_get() returns static allocated memory */ + env_value = has_env ? env_get("omnia_wwan_slot") : NULL; +#endif + + if (omnia_detect_wwan_usb3(env_value)) { + /* Disable SerDes for USB 3.0 pins on the front USB-A port */ + board_serdes_map[1].serdes_type = DEFAULT_SERDES; + /* Change SerDes for third mPCIe port (WWAN) from PCIe to USB 3.0 */ + board_serdes_map[4].serdes_type = USB3_HOST0; + board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS; + board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; + } + *serdes_map_array = board_serdes_map; *count = ARRAY_SIZE(board_serdes_map); @@ -597,12 +627,38 @@ static void fixup_msata_port_nodes(void *blob) } } +static void fixup_wwan_port_nodes(void *blob) +{ + bool mode_usb3; + + /* Determine if SerDes 4 is configured to USB3 mode */ + mode_usb3 = ((readl(MVEBU_REGISTER(0x183fc)) & GENMASK(19, 16)) >> 16) == 4; + + /* If SerDes 4 is not configured to USB3 mode then nothing is needed to fixup */ + if (!mode_usb3) + return; + + /* + * We're either adding status = "disabled" property, or changing + * status = "okay" to status = "disabled". In both cases we'll need more + * space. Increase the size a little. + */ + if (fdt_increase_size(blob, 32) < 0) { + printf("Cannot increase FDT size!\n"); + return; + } + + /* Disable PCIe port 2 DT node (WWAN) */ + disable_pcie_node(blob, 2); +} + #endif #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { fixup_msata_port_nodes(blob); + fixup_wwan_port_nodes(blob); return 0; } @@ -841,6 +897,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) { fixup_spi_nor_partitions(blob); fixup_msata_port_nodes(blob); + fixup_wwan_port_nodes(blob); return 0; } -- 2.20.1