Re: [PATCH v3 08/12] arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files

Kever Yang
2022-03-28T12:48:54Z

On 2022/3/4 07:52, Johan Jonker wrote:
> In order to sync rk3288.dtsi from Linux it needed to
> move all u-boot specific properties in separate dtsi files.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>
> Changed V3:
> add u-boot,dm-pre-reloc to noc node
> change reg size rk3288-u-boot.dtsi
>
> Changed V2:
> combine U-boot specific changes
> add bus_intmem label
> use current led node name
> ---
> arch/arm/dts/rk3288-evb-u-boot.dtsi | 11 +++
> arch/arm/dts/rk3288-evb.dts | 11 ---
> arch/arm/dts/rk3288-firefly-u-boot.dtsi | 31 +++++++
> arch/arm/dts/rk3288-firefly.dts | 17 ----
> arch/arm/dts/rk3288-firefly.dtsi | 3 -
> arch/arm/dts/rk3288-miqi-u-boot.dtsi | 20 +++++
> arch/arm/dts/rk3288-miqi.dts | 11 ---
> arch/arm/dts/rk3288-miqi.dtsi | 2 -
> arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi | 44 ++++++++++
> arch/arm/dts/rk3288-phycore-rdk.dts | 18 -----
> arch/arm/dts/rk3288-phycore-som.dtsi | 6 --
> arch/arm/dts/rk3288-popmetal-u-boot.dtsi | 11 +++
> arch/arm/dts/rk3288-popmetal.dts | 11 ---
> arch/arm/dts/rk3288-rock2-square-u-boot.dtsi | 30 +++++++
> arch/arm/dts/rk3288-rock2-square.dts | 18 -----
> arch/arm/dts/rk3288-u-boot.dtsi | 80 ++++++++++++++++---
> arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi | 14 ++++
> arch/arm/dts/rk3288-veyron-jerry.dts | 11 ---
> arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi | 14 ++++
> arch/arm/dts/rk3288-veyron-mickey.dts | 11 ---
> arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi | 14 ++++
> arch/arm/dts/rk3288-veyron-minnie.dts | 11 ---
> arch/arm/dts/rk3288-veyron-u-boot.dtsi | 62 ++++++++++++++
> arch/arm/dts/rk3288-veyron.dtsi | 39 ---------
> arch/arm/dts/rk3288.dtsi | 49 +-----------
> 25 files changed, 321 insertions(+), 228 deletions(-)
> create mode 100644 arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi
> index 8ac7840f..c8f51207 100644
> --- a/arch/arm/dts/rk3288-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi
> @@ -5,6 +5,17 @@
>
> #include "rk3288-u-boot.dtsi"
>
> +&dmc {
> + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> + 0x8 0x1f4>;
> + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> + 0x0 0xc3 0x6 0x2>;
> + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
> +};
> +
> &pinctrl {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
> index eac91a87..bb24a96c 100644
> --- a/arch/arm/dts/rk3288-evb.dts
> +++ b/arch/arm/dts/rk3288-evb.dts
> @@ -15,17 +15,6 @@
> };
> };
>
> -&dmc {
> - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> - 0x8 0x1f4>;
> - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> - 0x0 0xc3 0x6 0x2>;
> - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
> -};
> -
> &pwm1 {
> status = "okay";
> };
> diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
> index 8b9c3831..cc84d7c4 100644
> --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
> @@ -5,6 +5,37 @@
>
> #include "rk3288-u-boot.dtsi"
>
> +/ {
> + config {
> + u-boot,dm-pre-reloc;
> + u-boot,boot-led = "firefly:green:power";
> + };
> +
> + leds {
> + u-boot,dm-pre-reloc;
> +
> + work {
> + u-boot,dm-pre-reloc;
> + };
> +
> + power {
> + u-boot,dm-pre-reloc;
> + };
> + };
> +};
> +
> +&dmc {
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + /* Add a dummy value to cause of-platdata think this is bytes */
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> +};
> +
> &pinctrl {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
> index 1cff04e7..72982efd 100644
> --- a/arch/arm/dts/rk3288-firefly.dts
> +++ b/arch/arm/dts/rk3288-firefly.dts
> @@ -13,23 +13,6 @@
> chosen {
> stdout-path = &uart2;
> };
> -
> - config {
> - u-boot,dm-pre-reloc;
> - u-boot,boot-led = "firefly:green:power";
> - };
> -};
> -
> -&dmc {
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - /* Add a dummy value to cause of-platdata think this is bytes */
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> };
>
> &ir {
> diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
> index b7f279f7..1117d391 100644
> --- a/arch/arm/dts/rk3288-firefly.dtsi
> +++ b/arch/arm/dts/rk3288-firefly.dtsi
> @@ -37,11 +37,9 @@
> };
>
> leds {
> - u-boot,dm-pre-reloc;
> compatible = "gpio-leds";
>
> work {
> - u-boot,dm-pre-reloc;
> gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
> label = "firefly:blue:user";
> linux,default-trigger = "rc-feedback";
> @@ -50,7 +48,6 @@
> };
>
> power {
> - u-boot,dm-pre-reloc;
> gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
> label = "firefly:green:power";
> linux,default-trigger = "default-on";
> diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
> index 4f63fc9f..2a74fdd1 100644
> --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
> @@ -4,6 +4,26 @@
> */
>
> #include "rk3288-u-boot.dtsi"
> +/ {
> + leds {
> + u-boot,dm-pre-reloc;
> +
> + work {
> + u-boot,dm-pre-reloc;
> + };
> + };
> +};
> +
> +&dmc {
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> +};
>
> &pinctrl {
> u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
> index e47170c6..4a2f249e 100644
> --- a/arch/arm/dts/rk3288-miqi.dts
> +++ b/arch/arm/dts/rk3288-miqi.dts
> @@ -14,14 +14,3 @@
> stdout-path = "serial2:115200n8";
> };
> };
> -
> -&dmc {
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> -};
> diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
> index 432f744b..cb80cbf2 100644
> --- a/arch/arm/dts/rk3288-miqi.dtsi
> +++ b/arch/arm/dts/rk3288-miqi.dtsi
> @@ -34,11 +34,9 @@
>
>
> leds {
> - u-boot,dm-pre-reloc;
> compatible = "gpio-leds";
>
> work {
> - u-boot,dm-pre-reloc;
> gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
> label = "miqi:green:user";
> linux,default-trigger = "default-on";
> diff --git a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
> new file mode 100644
> index 00000000..30f4cb10
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include "rk3288-u-boot.dtsi"
> +
> +&dmc {
> + rockchip,num-channels = <2>;
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
> +};
> +
> +&emmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c0 {
> + u-boot,dm-pre-reloc;
> +
> + rk818: pmic@1c {
> + u-boot,dm-pre-reloc;
> +
> + regulators {
> + u-boot,dm-pre-reloc;
> + };
> + };
> +};
> +
> +&pinctrl {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart2 {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
> index cc392109..ebea8e67 100644
> --- a/arch/arm/dts/rk3288-phycore-rdk.dts
> +++ b/arch/arm/dts/rk3288-phycore-rdk.dts
> @@ -112,19 +112,6 @@
> };
> };
>
> -&dmc {
> - rockchip,num-channels = <2>;
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
> -};
> -
> &gmac {
> status = "okay";
> };
> @@ -175,8 +162,6 @@
> };
>
> &pinctrl {
> - u-boot,dm-pre-reloc;
> -
> pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
> bias-pull-up;
> drive-strength = <12>;
> @@ -246,8 +231,6 @@
> };
>
> &sdmmc {
> - u-boot,dm-pre-reloc;
> -
> bus-width = <4>;
> cap-mmc-highspeed;
> cap-sd-highspeed;
> @@ -268,7 +251,6 @@
> };
>
> &uart2 {
> - u-boot,dm-pre-reloc;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
> index 02d11968..821525f7 100644
> --- a/arch/arm/dts/rk3288-phycore-som.dtsi
> +++ b/arch/arm/dts/rk3288-phycore-som.dtsi
> @@ -149,8 +149,6 @@
>
> &emmc {
> status = "okay";
> - u-boot,dm-pre-reloc;
> -
> bus-width = <8>;
> cap-mmc-highspeed;
> disable-wp;
> @@ -201,8 +199,6 @@
>
> &i2c0 {
> status = "okay";
> - u-boot,dm-pre-reloc;
> -
> clock-frequency = <400000>;
>
> rk818: pmic@1c {
> @@ -216,7 +212,6 @@
> rockchip,system-power-controller;
> wakeup-source;
> #clock-cells = <1>;
> - u-boot,dm-pre-reloc;
>
> vcc1-supply = <&vdd_sys>;
> vcc2-supply = <&vdd_sys>;
> @@ -230,7 +225,6 @@
> vddio-supply = <&vdd_3v3_io>;
>
> regulators {
> - u-boot,dm-pre-reloc;
> vdd_log: DCDC_REG1 {
> regulator-name = "vdd_log";
> regulator-always-on;
> diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
> index 8ac7840f..3782253c 100644
> --- a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
> @@ -5,6 +5,17 @@
>
> #include "rk3288-u-boot.dtsi"
>
> +&dmc {
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> +};
> +
> &pinctrl {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
> index 5c6d06f2..736dc51e 100644
> --- a/arch/arm/dts/rk3288-popmetal.dts
> +++ b/arch/arm/dts/rk3288-popmetal.dts
> @@ -15,17 +15,6 @@
> };
> };
>
> -&dmc {
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> -};
> -
> &pwm1 {
> status = "okay";
> };
> diff --git a/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
> new file mode 100644
> index 00000000..509f789b
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include "rk3288-u-boot.dtsi"
> +
> +&dmc {
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> +};
> +
> +&gpio7 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&pinctrl {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart2 {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
> index 11c580a0..41676696 100644
> --- a/arch/arm/dts/rk3288-rock2-square.dts
> +++ b/arch/arm/dts/rk3288-rock2-square.dts
> @@ -96,7 +96,6 @@
> };
>
> &sdmmc {
> - u-boot,dm-pre-reloc;
> bus-width = <4>;
> cap-mmc-highspeed;
> cap-sd-highspeed;
> @@ -139,7 +138,6 @@
> };
>
> &pinctrl {
> - u-boot,dm-pre-reloc;
> ir {
> ir_int: ir-int {
> rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
> @@ -171,7 +169,6 @@
>
> &uart2 {
> status = "okay";
> - u-boot,dm-pre-reloc;
> reg-shift = <2>;
> };
>
> @@ -182,18 +179,3 @@
> &usb_host0_ehci {
> status = "okay";
> };
> -
> -&dmc {
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> -};
> -
> -&gpio7 {
> - u-boot,dm-pre-reloc;
> -};
> diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
> index e3c6c10f..9eb696b1 100644
> --- a/arch/arm/dts/rk3288-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-u-boot.dtsi
> @@ -7,10 +7,53 @@
> #include "rockchip-optee.dtsi"
>
> / {
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + gpio4 = &gpio4;
> + gpio5 = &gpio5;
> + gpio6 = &gpio6;
> + gpio7 = &gpio7;
> + gpio8 = &gpio8;
> + mmc0 = &emmc;
> + mmc1 = &sdmmc;
> + mmc2 = &sdio0;
> + mmc3 = &sdio1;
> + };
> +
> chosen {
> u-boot,spl-boot-order = \
> "same-as-spl", &emmc, &sdmmc;
> };
> +
> + dmc: dmc@ff610000 {
> + compatible = "rockchip,rk3288-dmc", "syscon";
> + reg = <0xff610000 0x3fc
> + 0xff620000 0x294
> + 0xff630000 0x3fc
> + 0xff640000 0x294>;
> + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
> + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
> + <&cru ARMCLK>;
> + clock-names = "pclk_ddrupctl0", "pclk_publ0",
> + "pclk_ddrupctl1", "pclk_publ1",
> + "arm_clk";
> + rockchip,cru = <&cru>;
> + rockchip,grf = <&grf>;
> + rockchip,noc = <&noc>;
> + rockchip,pmu = <&pmu>;
> + rockchip,sgrf = <&sgrf>;
> + rockchip,sram = <&ddr_sram>;
> + u-boot,dm-pre-reloc;
> + };
> +
> + noc: syscon@ffac0000 {
> + compatible = "rockchip,rk3288-noc", "syscon";
> + reg = <0xffac0000 0x2000>;
> + u-boot,dm-pre-reloc;
> + };
> };
>
> #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
> @@ -37,38 +80,53 @@
> };
> #endif
>
> -&dmc {
> - u-boot,dm-pre-reloc;
> +&bus_intmem {
> + ddr_sram: ddr-sram@1000 {
> + compatible = "rockchip,rk3288-ddr-sram";
> + reg = <0x1000 0x4000>;
> + };
> };
>
> -&pmu {
> +&cru {
> u-boot,dm-pre-reloc;
> };
>
> -&sgrf {
> +&gpio7 {
> u-boot,dm-pre-reloc;
> };
>
> -&cru {
> +&grf {
> u-boot,dm-pre-reloc;
> };
>
> -&grf {
> +&pmu {
> u-boot,dm-pre-reloc;
> };
>
> -&vopb {
> +&sgrf {
> u-boot,dm-pre-reloc;
> };
>
> -&vopl {
> - u-boot,dm-pre-reloc;
> +&uart0 {
> + clock-frequency = <24000000>;
> +};
> +
> +&uart1 {
> + clock-frequency = <24000000>;
> };
>
> -&noc {
> +&uart2 {
> + clock-frequency = <24000000>;
> +};
> +
> +&uart3 {
> + clock-frequency = <24000000>;
> +};
> +
> +&vopb {
> u-boot,dm-pre-reloc;
> };
>
> -&gpio7 {
> +&vopl {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
> new file mode 100644
> index 00000000..2cc6b090
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include "rk3288-veyron-u-boot.dtsi"
> +
> +&dmc {
> + rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
> + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> + 0x5 0x0>;
> + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> + 0xa60 0x40 0x10 0x0>;
> + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
> index c251d9d5..ff7669eb 100644
> --- a/arch/arm/dts/rk3288-veyron-jerry.dts
> +++ b/arch/arm/dts/rk3288-veyron-jerry.dts
> @@ -66,17 +66,6 @@
> };
> };
>
> -&dmc {
> - rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
> - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
> - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
> - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
> - 0x5 0x0>;
> - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
> - 0xa60 0x40 0x10 0x0>;
> - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
> -};
> -
> &gpio_keys {
> power {
> gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
> diff --git a/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
> new file mode 100644
> index 00000000..213a46ba
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include "rk3288-veyron-u-boot.dtsi"
> +
> +&dmc {
> + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> + 0x8 0x1f4>;
> + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> + 0x0 0xc3 0x6 0x2>;
> + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
> index e0dc3620..0521d9e0 100644
> --- a/arch/arm/dts/rk3288-veyron-mickey.dts
> +++ b/arch/arm/dts/rk3288-veyron-mickey.dts
> @@ -161,17 +161,6 @@
> };
> };
>
> -&dmc {
> - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> - 0x8 0x1f4>;
> - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> - 0x0 0xc3 0x6 0x2>;
> - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
> -};
> -
> &emmc {
> /delete-property/mmc-hs200-1_8v;
> };
> diff --git a/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
> new file mode 100644
> index 00000000..8211da41
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include "rk3288-veyron-u-boot.dtsi"
> +
> +&dmc {
> + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> + 0x8 0x1f4>;
> + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> + 0x0 0xc3 0x6 0x1>;
> + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts
> index 646f6ae7..b56a3f4f 100644
> --- a/arch/arm/dts/rk3288-veyron-minnie.dts
> +++ b/arch/arm/dts/rk3288-veyron-minnie.dts
> @@ -137,17 +137,6 @@
> power-supply = <&backlight_regulator>;
> };
>
> -&dmc {
> - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> - 0x8 0x1f4>;
> - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> - 0x0 0xc3 0x6 0x1>;
> - rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
> -};
> -
> &emmc {
> /delete-property/mmc-hs200-1_8v;
> };
> diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
> index 899fe6e7..c8b33fea 100644
> --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
> @@ -5,7 +5,69 @@
>
> #include "rk3288-u-boot.dtsi"
>
> +/ {
> + chosen {
> + u-boot,spl-boot-order = &spi_flash;
> + };
> +};
> +
> +&dmc {
> + logic-supply = <&vdd_logic>;
> + rockchip,odt-disable-freq = <333000000>;
> + rockchip,dll-disable-freq = <333000000>;
> + rockchip,sr-enable-freq = <333000000>;
> + rockchip,pd-enable-freq = <666000000>;
> + rockchip,auto-self-refresh-cnt = <0>;
> + rockchip,auto-power-down-cnt = <64>;
> + rockchip,ddr-speed-bin = <21>;
> + rockchip,trcd = <10>;
> + rockchip,trp = <10>;
> + operating-points = <
> + /* KHz uV */
> + 200000 1050000
> + 333000 1100000
> + 533000 1150000
> + 666000 1200000
> + >;
> +};
> +
> +&gpio3 {
> + u-boot,dm-pre-reloc;
> +};
> +
> &gpio7 {
> u-boot,dm-pre-reloc;
> };
>
> +&gpio8 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c0 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&pinctrl {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&rk808 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&spi2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&spi_flash {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index 8754043b..4a9c27a4 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -16,7 +16,6 @@
>
> chosen {
> stdout-path = &uart2;
> - u-boot,spl-boot-order = &spi_flash;
> };
>
> firmware {
> @@ -220,26 +219,6 @@
> cpu0-supply = <&vdd_cpu>;
> };
>
> -&dmc {
> - logic-supply = <&vdd_logic>;
> - rockchip,odt-disable-freq = <333000000>;
> - rockchip,dll-disable-freq = <333000000>;
> - rockchip,sr-enable-freq = <333000000>;
> - rockchip,pd-enable-freq = <666000000>;
> - rockchip,auto-self-refresh-cnt = <0>;
> - rockchip,auto-power-down-cnt = <64>;
> - rockchip,ddr-speed-bin = <21>;
> - rockchip,trcd = <10>;
> - rockchip,trp = <10>;
> - operating-points = <
> - /* KHz uV */
> - 200000 1050000
> - 333000 1100000
> - 533000 1150000
> - 666000 1200000
> - >;
> -};
> -
> &efuse {
> status = "okay";
> };
> @@ -299,10 +278,8 @@
>
> &spi2 {
> status = "okay";
> - u-boot,dm-pre-reloc;
>
> spi_flash: spiflash@0 {
> - u-boot,dm-pre-reloc;
> compatible = "spidev", "jedec,spi-nor";
> spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
> reg = <0>;
> @@ -315,7 +292,6 @@
> clock-frequency = <400000>;
> i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
> i2c-scl-rising-time-ns = <100>; /* 45ns measured */
> - u-boot,dm-pre-reloc;
>
> rk808: pmic@1b {
> compatible = "rockchip,rk808";
> @@ -328,7 +304,6 @@
> rockchip,system-power-controller;
> wakeup-source;
> #clock-cells = <1>;
> - u-boot,dm-pre-reloc;
>
> vcc1-supply = <&vcc33_sys>;
> vcc2-supply = <&vcc33_sys>;
> @@ -557,7 +532,6 @@
>
> &uart2 {
> status = "okay";
> - u-boot,dm-pre-reloc;
> reg-shift = <2>;
> };
>
> @@ -601,7 +575,6 @@
> };
>
> &pinctrl {
> - u-boot,dm-pre-reloc;
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <
> /* Common for sleep and wake, but no owners */
> @@ -826,15 +799,3 @@
> assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
> assigned-clock-parents = <&cru SCLK_OTGPHY0>;
> };
> -
> -&sdmmc {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&gpio3 {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&gpio8 {
> - u-boot,dm-pre-reloc;
> -};
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 2086dbfd..c4abfa37 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -15,25 +15,12 @@
>
> interrupt-parent = <&gic>;
> aliases {
> - gpio0 = &gpio0;
> - gpio1 = &gpio1;
> - gpio2 = &gpio2;
> - gpio3 = &gpio3;
> - gpio4 = &gpio4;
> - gpio5 = &gpio5;
> - gpio6 = &gpio6;
> - gpio7 = &gpio7;
> - gpio8 = &gpio8;
> i2c0 = &i2c0;
> i2c1 = &i2c1;
> i2c2 = &i2c2;
> i2c3 = &i2c3;
> i2c4 = &i2c4;
> i2c5 = &i2c5;
> - mmc0 = &emmc;
> - mmc1 = &sdmmc;
> - mmc2 = &sdio0;
> - mmc3 = &sdio1;
> mshc0 = &emmc;
> mshc1 = &sdmmc;
> mshc2 = &sdio0;
> @@ -323,7 +310,6 @@
> interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clock-frequency = <24000000>;
> clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> clock-names = "baudclk", "apb_pclk";
> pinctrl-names = "default";
> @@ -337,7 +323,6 @@
> interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clock-frequency = <24000000>;
> clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> clock-names = "baudclk", "apb_pclk";
> pinctrl-names = "default";
> @@ -351,7 +336,6 @@
> interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clock-frequency = <24000000>;
> clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> clock-names = "baudclk", "apb_pclk";
> pinctrl-names = "default";
> @@ -364,7 +348,6 @@
> interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clock-frequency = <24000000>;
> clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> clock-names = "baudclk", "apb_pclk";
> pinctrl-names = "default";
> @@ -378,7 +361,6 @@
> interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clock-frequency = <24000000>;
> clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> clock-names = "baudclk", "apb_pclk";
> pinctrl-names = "default";
> @@ -476,26 +458,6 @@
> status = "disabled";
> };
>
> - dmc: dmc@ff610000 {
> - compatible = "rockchip,rk3288-dmc", "syscon";
> - rockchip,cru = <&cru>;
> - rockchip,grf = <&grf>;
> - rockchip,pmu = <&pmu>;
> - rockchip,sgrf = <&sgrf>;
> - rockchip,noc = <&noc>;
> - reg = <0xff610000 0x3fc
> - 0xff620000 0x294
> - 0xff630000 0x3fc
> - 0xff640000 0x294>;
> - rockchip,sram = <&ddr_sram>;
> - clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
> - <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
> - <&cru ARMCLK>;
> - clock-names = "pclk_ddrupctl0", "pclk_publ0",
> - "pclk_ddrupctl1", "pclk_publ1",
> - "arm_clk";
> - };
> -
> i2c0: i2c@ff650000 {
> compatible = "rockchip,rk3288-i2c";
> reg = <0xff650000 0x1000>;
> @@ -570,7 +532,7 @@
> status = "disabled";
> };
>
> - bus_intmem@ff700000 {
> + bus_intmem: bus_intmem@ff700000 {
> compatible = "mmio-sram";
> reg = <0xff700000 0x18000>;
> #address-cells = <1>;
> @@ -580,10 +542,6 @@
> compatible = "rockchip,rk3066-smp-sram";
> reg = <0x00 0x10>;
> };
> - ddr_sram: ddr-sram@1000 {
> - compatible = "rockchip,rk3288-ddr-sram";
> - reg = <0x1000 0x4000>;
> - };
> };
>
> sram@ff720000 {
> @@ -912,11 +870,6 @@
> status = "disabled";
> };
>
> - noc: syscon@ffac0000 {
> - compatible = "rockchip,rk3288-noc", "syscon";
> - reg = <0xffac0000 0x2000>;
> - };
> -
> efuse: efuse@ffb40000 {
> compatible = "rockchip,rk3288-efuse";
> reg = <0xffb40000 0x10000>;