[PATCH v3 03/12] arm: dts: rockchip: move all rk322x u-boot specific properties in separate dtsi files

Johan Jonker
2022-03-03T23:53:20Z

In order to sync rk322x.dtsi from Linux, move all
U-boot specific properties in separate dtsi files.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changed V3:
add include "rockchip-u-boot.dtsi"
---
arch/arm/dts/rk3229-evb-u-boot.dtsi | 28 +++++++++++++++
arch/arm/dts/rk3229-evb.dts | 17 ---------
arch/arm/dts/rk322x-u-boot.dtsi | 56 +++++++++++++++++++++++++++++
arch/arm/dts/rk322x.dtsi | 37 -------------------
4 files changed, 84 insertions(+), 54 deletions(-)
create mode 100644 arch/arm/dts/rk3229-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk322x-u-boot.dtsi

diff --git a/arch/arm/dts/rk3229-evb-u-boot.dtsi b/arch/arm/dts/rk3229-evb-u-boot.dtsi
new file mode 100644
index 00000000..b65149c2
--- /dev/null
+++ b/arch/arm/dts/rk3229-evb-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk322x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
+ 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
+ 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
+ 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
+ 0x0 0x924>;
+ rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
+ rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
+ 0 300 3 0 120>;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 632cdc9b..66a3ba23 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -11,10 +11,6 @@
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";

- chosen {
- stdout-path = &uart2;
- };
-
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
@@ -38,17 +34,6 @@
};
};

-&dmc {
- rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
- 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
- 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
- 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
- 0x0 0x924>;
- rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
- rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
- 0 300 3 0 120>;
-};
-
&gmac {
assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
@@ -66,7 +51,6 @@
};

&emmc {
- u-boot,dm-pre-reloc;
status = "okay";
};

@@ -82,7 +66,6 @@
};

&uart2 {
- u-boot,dm-pre-reloc;
status = "okay";
};

diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi
new file mode 100644
index 00000000..79c41e48
--- /dev/null
+++ b/arch/arm/dts/rk322x-u-boot.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x9000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x9000>;
+
+ smp-sram@0 {
+ compatible = "rockchip,rk322x-smp-sram";
+ reg = <0x00 0x10>;
+ };
+
+ ddr_sram: ddr-sram@1000 {
+ compatible = "rockchip,rk322x-ddr-sram";
+ reg = <0x1000 0x8000>;
+ };
+ };
+
+ dmc: dmc@11200000 {
+ compatible = "rockchip,rk3228-dmc", "syscon";
+ reg = <0x11200000 0x3fc
+ 0x12000000 0x400>;
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ rockchip,sram = <&ddr_sram>;
+ u-boot,dm-pre-reloc;
+ };
+
+ service_msch: syscon@31090000 {
+ compatible = "rockchip,rk3228-msch", "syscon";
+ reg = <0x31090000 0x2000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ max-frequency = <150000000>;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ max-frequency = <150000000>;
+};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 4a8be5da..3245da3c 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -107,22 +107,6 @@
#clock-cells = <0>;
};

- bus_intmem@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x9000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x10080000 0x9000>;
- smp-sram@0 {
- compatible = "rockchip,rk322x-smp-sram";
- reg = <0x00 0x10>;
- };
- ddr_sram: ddr-sram@1000 {
- compatible = "rockchip,rk322x-ddr-sram";
- reg = <0x1000 0x8000>;
- };
- };
-
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
@@ -165,7 +149,6 @@
};

grf: syscon@11000000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-grf", "syscon";
reg = <0x11000000 0x1000>;
};
@@ -317,7 +300,6 @@
};

cru: clock-controller@110e0000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
rockchip,grf = <&grf>;
@@ -387,7 +369,6 @@
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
- max-frequency = <150000000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -414,7 +395,6 @@
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
- max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
@@ -768,21 +748,4 @@
};
};
};
-
- dmc: dmc@11200000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3228-dmc", "syscon";
- rockchip,cru = <&cru>;
- rockchip,grf = <&grf>;
- rockchip,msch = <&service_msch>;
- reg = <0x11200000 0x3fc
- 0x12000000 0x400>;
- rockchip,sram = <&ddr_sram>;
- };
-
- service_msch: syscon@31090000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3228-msch", "syscon";
- reg = <0x31090000 0x2000>;
- };
};
--
2.20.1