Re: [PATCH v3 11/12] arm: dts: rockchip: sync rk3288-veyron DT from Linux

Kever Yang
2022-03-28T12:50:53Z

On 2022/3/4 07:52, Johan Jonker wrote:
> Sync rk3288-veyron DT from Linux version 5.17.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>
> Changed V3:
> update
> change reg size
>
> Changed V2:
> update
> add label spi_flash veyron
> ---
> arch/arm/dts/rk3288-veyron-analog-audio.dtsi | 99 +++
> .../dts/rk3288-veyron-broadcom-bluetooth.dtsi | 22 +
> arch/arm/dts/rk3288-veyron-chromebook.dtsi | 115 ++--
> arch/arm/dts/rk3288-veyron-edp.dtsi | 141 ++++
> arch/arm/dts/rk3288-veyron-jerry.dts | 506 +++++++++++---
> arch/arm/dts/rk3288-veyron-mickey.dts | 343 +++++++---
> arch/arm/dts/rk3288-veyron-minnie.dts | 441 +++++++-----
> arch/arm/dts/rk3288-veyron-sdmmc.dtsi | 89 +++
> arch/arm/dts/rk3288-veyron-speedy.dts | 303 ++++++--
> arch/arm/dts/rk3288-veyron.dtsi | 645 ++++++------------
> 10 files changed, 1799 insertions(+), 905 deletions(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-analog-audio.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-edp.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-sdmmc.dtsi
>
> diff --git a/arch/arm/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/dts/rk3288-veyron-analog-audio.dtsi
> new file mode 100644
> index 00000000..51208d16
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-analog-audio.dtsi
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Google Veyron (and derivatives) fragment for the max98090 audio
> + * codec and analog headphone jack.
> + *
> + * Copyright 2016 Google, Inc
> + */
> +
> +/ {
> + sound {
> + compatible = "rockchip,rockchip-audio-max98090";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mic_det>, <&hp_det>;
> + rockchip,model = "VEYRON-I2S";
> + rockchip,i2s-controller = <&i2s>;
> + rockchip,audio-codec = <&max98090>;
> + rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
> + rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
> + rockchip,headset-codec = <&headsetcodec>;
> + rockchip,hdmi-codec = <&hdmi>;
> + };
> +};
> +
> +&i2c2 {
> + max98090: max98090@10 {
> + compatible = "maxim,max98090";
> + reg = <0x10>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
> + clock-names = "mclk";
> + clocks = <&cru SCLK_I2S0_OUT>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&int_codec>;
> + };
> +};
> +
> +&i2c4 {
> + headsetcodec: ts3a227e@3b {
> + compatible = "ti,ts3a227e";
> + reg = <0x3b>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ts3a227e_int_l>;
> + ti,micbias = <7>; /* MICBIAS = 2.8V */
> + };
> +};
> +
> +&i2s {
> + status = "okay";
> +};
> +
> +&io_domains {
> + audio-supply = <&vcc18_codec>;
> +};
> +
> +&rk808 {
> + vcc10-supply = <&vcc33_sys>;
> +
> + regulators {
> + vcc18_codec: LDO_REG6 {
> + regulator-name = "vcc18_codec";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> + };
> +};
> +
> +&pinctrl {
> + codec {
> + hp_det: hp-det {
> + rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> +
> + /*
> + * HACK: We're going to _pull down_ this _active low_ interrupt
> + * so that it never fires. We don't need this interrupt because
> + * we've got a ts3a227e chip but the driver requires it.
> + */
> + int_codec: int-codec {
> + rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> +
> + mic_det: mic-det {
> + rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + headset {
> + ts3a227e_int_l: ts3a227e-int-l {
> + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
> new file mode 100644
> index 00000000..a10d25ac
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
> + * chip.
> + *
> + * Copyright 2019 Google, Inc
> + */
> +
> +&uart0 {
> + bluetooth {
> + pinctrl-names = "default";
> + pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
> + <&bt_dev_wake>;
> +
> + compatible = "brcm,bcm43540-bt";
> + host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
> + shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
> + device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
> + max-speed = <3000000>;
> + brcm,bt-pcm-int-params = [01 02 00 01 01];
> + };
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
> index 143eaae2..05112c25 100644
> --- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
> +++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
> @@ -1,39 +1,45 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Google Veyron (and derivatives) board device tree source
> + * Chromebook specific parts
> *
> - * Copyright 2014 Google, Inc
> + * Copyright 2015 Google, Inc
> */
>
> #include <dt-bindings/clock/rockchip,rk808.h>
> #include <dt-bindings/input/input.h>
> #include "rk3288-veyron.dtsi"
> +#include "rk3288-veyron-analog-audio.dtsi"
> +#include "rk3288-veyron-edp.dtsi"
> +#include "rk3288-veyron-sdmmc.dtsi"
>
> / {
> aliases {
> + /* Assign 20 so we don't get confused w/ builtin ones */
> i2c20 = &i2c_tunnel;
> - video0 = &vopl;
> - video1 = &vopb;
> - };
> -
> - gpio_keys: gpio-keys {
> - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
> - lid {
> - label = "Lid";
> - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
> - linux,code = <0>; /* SW_LID */
> - linux,input-type = <5>; /* EV_SW */
> - debounce-interval = <1>;
> - gpio-key,wakeup;
> - };
> };
>
> gpio-charger {
> compatible = "gpio-charger";
> - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
> + charger-type = "mains";
> + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&ac_present_ap>;
> - charger-type = "mains";
> + };
> +
> + lid_switch: lid-switch {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&ap_lid_int_l>;
> +
> + lid {
> + label = "Lid";
> + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> + linux,code = <SW_LID>;
> + linux,input-type = <EV_SW>;
> + debounce-interval = <1>;
> + };
> };
>
> /* A non-regulated voltage from power supply or battery */
> @@ -56,7 +62,7 @@
> vcc5_host1: vcc5-host1-regulator {
> compatible = "regulator-fixed";
> enable-active-high;
> - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&host1_pwr_en>;
> regulator-name = "vcc5_host1";
> @@ -68,7 +74,7 @@
> vcc5v_otg: vcc5v-otg-regulator {
> compatible = "regulator-fixed";
> enable-active-high;
> - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&usbotg_pwren_h>;
> regulator-name = "vcc5_host2";
> @@ -78,34 +84,34 @@
> };
>
> &rk808 {
> + vcc11-supply = <&vcc_5v>;
> +
> regulators {
> vcc33_ccd: LDO_REG8 {
> + regulator-name = "vcc33_ccd";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> - regulator-name = "vcc33_ccd";
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
> };
> };
>
> &spi0 {
> status = "okay";
> - spi-activate-delay = <100>;
> - spi-max-frequency = <3000000>;
> - spi-deactivate-delay = <200>;
>
> cros_ec: ec@0 {
> compatible = "google,cros-ec-spi";
> - spi-max-frequency = <3000000>;
> + reg = <0>;
> + google,cros-ec-spi-pre-delay = <30>;
> interrupt-parent = <&gpio7>;
> - interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
> - ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>;
> + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
> pinctrl-names = "default";
> pinctrl-0 = <&ec_int>;
> - reg = <0>;
> - google,cros-ec-spi-pre-delay = <30>;
> + spi-max-frequency = <3000000>;
>
> i2c_tunnel: i2c-tunnel {
> compatible = "google,cros-ec-i2c-tunnel";
> @@ -118,86 +124,59 @@
>
> &i2c4 {
> trackpad@15 {
> - compatible = "elan,i2c_touchpad";
> + compatible = "elan,ekth3000";
> + reg = <0x15>;
> interrupt-parent = <&gpio7>;
> - interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> + interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
> pinctrl-names = "default";
> pinctrl-0 = <&trackpad_int>;
> - reg = <0x15>;
> vcc-supply = <&vcc33_io>;
> wakeup-source;
> };
> };
>
> &pinctrl {
> - pinctrl-0 = <
> - /* Common for sleep and wake, but no owners */
> - &ddr0_retention
> - &ddrio_pwroff
> - &global_pwroff
> -
> - /* Wake only */
> - &suspend_l_wake
> - &bt_dev_wake_awake
> - >;
> - pinctrl-1 = <
> - /* Common for sleep and wake, but no owners */
> - &ddr0_retention
> - &ddrio_pwroff
> - &global_pwroff
> -
> - /* Sleep only */
> - &suspend_l_sleep
> - &bt_dev_wake_sleep
> - >;
> -
> buttons {
> ap_lid_int_l: ap-lid-int-l {
> - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> charger {
> ac_present_ap: ac-present-ap {
> - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> cros-ec {
> ec_int: ec-int {
> - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - sdmmc {
> - sdmmc_wp_gpio: sdmmc-wp-gpio {
> - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> suspend {
> suspend_l_wake: suspend-l-wake {
> - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>;
> + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
> };
>
> suspend_l_sleep: suspend-l-sleep {
> - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>;
> + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
> };
> };
>
> trackpad {
> trackpad_int: trackpad-int {
> - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> usb-host {
> host1_pwr_en: host1-pwr-en {
> - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
> };
>
> usbotg_pwren_h: usbotg-pwren-h {
> - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
> };
> diff --git a/arch/arm/dts/rk3288-veyron-edp.dtsi b/arch/arm/dts/rk3288-veyron-edp.dtsi
> new file mode 100644
> index 00000000..32c0f107
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-edp.dtsi
> @@ -0,0 +1,141 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Veyron (and derivatives) fragment for the edp displays
> + *
> + * Copyright 2019 Google LLC
> + */
> +
> +/ {
> + backlight_regulator: backlight-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_pwr_en>;
> + regulator-name = "backlight_regulator";
> + vin-supply = <&vcc33_sys>;
> + startup-delay-us = <15000>;
> + };
> +
> + panel_regulator: panel-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_enable_h>;
> + regulator-name = "panel_regulator";
> + vin-supply = <&vcc33_sys>;
> + };
> +
> + vcc18_lcd: vcc18-lcd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&avdd_1v8_disp_en>;
> + regulator-name = "vcc18_lcd";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc18_wl>;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + brightness-levels = <0 255>;
> + num-interpolated-steps = <255>;
> + default-brightness-level = <128>;
> + enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_en>;
> + pwms = <&pwm0 0 1000000 0>;
> + post-pwm-on-delay-ms = <10>;
> + pwm-off-delay-ms = <10>;
> + power-supply = <&backlight_regulator>;
> + };
> +
> + panel: panel {
> + compatible = "innolux,n116bge";
> + status = "okay";
> + power-supply = <&panel_regulator>;
> + backlight = <&backlight>;
> +
> + panel-timing {
> + clock-frequency = <74250000>;
> + hactive = <1366>;
> + hfront-porch = <136>;
> + hback-porch = <60>;
> + hsync-len = <30>;
> + hsync-active = <0>;
> + vactive = <768>;
> + vfront-porch = <8>;
> + vback-porch = <12>;
> + vsync-len = <12>;
> + vsync-active = <0>;
> + };
> +
> + ports {
> + panel_in: port {
> + panel_in_edp: endpoint {
> + remote-endpoint = <&edp_out_panel>;
> + };
> + };
> + };
> + };
> +};
> +
> +&edp {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_hpd>;
> +
> + ports {
> + edp_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_out_panel: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&panel_in_edp>;
> + };
> + };
> + };
> +};
> +
> +&edp_phy {
> + status = "okay";
> +};
> +
> +&pwm0 {
> + status = "okay";
> +};
> +
> +&vopl {
> + status = "okay";
> +};
> +
> +&vopl_mmu {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + backlight {
> + bl_pwr_en: bl_pwr_en {
> + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + bl_en: bl-en {
> + rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + lcd {
> + lcd_enable_h: lcd-en {
> + rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + avdd_1v8_disp_en: avdd-1v8-disp-en {
> + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
> index 40fee55c..2c916c50 100644
> --- a/arch/arm/dts/rk3288-veyron-jerry.dts
> +++ b/arch/arm/dts/rk3288-veyron-jerry.dts
> @@ -1,8 +1,8 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Google Veyron Jerry Rev 3+ board device tree source
> *
> - * Copyright 2014 Google, Inc
> + * Copyright 2015 Google, Inc
> */
>
> /dts-v1/;
> @@ -11,162 +11,454 @@
>
> / {
> model = "Google Jerry";
> - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
> + compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
> + "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
> + "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
> + "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
> "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
> "google,veyron-jerry-rev3", "google,veyron-jerry",
> "google,veyron", "rockchip,rk3288";
> -
> - chosen {
> - stdout-path = &uart2;
> - };
> -
> - panel_regulator: panel-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&lcd_enable_h>;
> - regulator-name = "panel_regulator";
> - vin-supply = <&vcc33_sys>;
> - };
> -
> - vcc18_lcd: vcc18-lcd {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&avdd_1v8_disp_en>;
> - regulator-name = "vcc18_lcd";
> - regulator-always-on;
> - regulator-boot-on;
> - vin-supply = <&vcc18_wl>;
> - };
> -
> - backlight_regulator: backlight-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&bl_pwr_en>;
> - regulator-name = "backlight_regulator";
> - vin-supply = <&vcc33_sys>;
> - startup-delay-us = <15000>;
> - };
> -
> - sound {
> - compatible = "rockchip,audio-max98090-jerry";
> -
> - cpu {
> - sound-dai = <&i2s 0>;
> - };
> -
> - codec {
> - sound-dai = <&max98090 0>;
> - };
> - };
> -};
> -
> -&gpio_keys {
> - power {
> - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
> - };
> -};
> -
> -&backlight {
> - power-supply = <&backlight_regulator>;
> -};
> -
> -&panel {
> - power-supply= <&panel_regulator>;
> };
>
> &rk808 {
> pinctrl-names = "default";
> pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
> - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
> - <&gpio7 15 GPIO_ACTIVE_HIGH>;
> + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
> + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
>
> regulators {
> mic_vcc: LDO_REG2 {
> + regulator-name = "mic_vcc";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <1800000>;
> regulator-max-microvolt = <1800000>;
> - regulator-name = "mic_vcc";
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
> };
> };
>
> +&sdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mwifiex: wifi@1 {
> + compatible = "marvell,sd8897";
> + reg = <1>;
> +
> + marvell,caldata-txpwrlimit-2g = /bits/ 8 <
> +0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
> +0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
> +0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
> +0x0d 0x09 0x0e 0x09 0x0f 0x09>;
> +
> + marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
> +0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
> +0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
> +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
> +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
> +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
> +0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
> +0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
> +0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
> +0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
> +0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
> +0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
> +0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
> +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
> +0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
> +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
> +0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
> +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
> +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
> +0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
> +0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
> +0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
> +0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
> +0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
> +0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
> +0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
> +0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
> +0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
> +0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
> +0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
> +
> + marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
> +0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
> +0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
> +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
> +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
> +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
> +0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
> +0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
> +0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
> +0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
> +0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
> +0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
> +0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
> +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
> +0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
> +0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
> +0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
> +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
> +0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
> +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
> +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
> +0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
> +0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
> +0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
> +0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
> +0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
> +0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
> +0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
> +0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
> +0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
> +0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
> +0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
> +0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
> +0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
> +0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
> +0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
> +0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
> +0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
> +0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
> +0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
> +0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
> +0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
> +0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
> +0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
> +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
> +
> + marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
> +0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
> +0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
> +0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
> +0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
> +0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
> +0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
> +0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
> +0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
> +0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
> +0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
> +0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
> +0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
> +0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
> +0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
> +0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
> +0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
> +0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
> +0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
> +0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
> +0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
> +0x1a 0x05 0x1b 0x05>;
> + };
> +};
> +
> &sdmmc {
> + disable-wp;
> pinctrl-names = "default";
> - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
> &sdmmc_bus4>;
> - disable-wp;
> };
>
> &vcc_5v {
> enable-active-high;
> - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&drv_5v>;
> };
>
> &vcc50_hdmi {
> enable-active-high;
> - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&vcc50_hdmi_en>;
> };
>
> -&edp {
> - pinctrl-names = "default";
> - pinctrl-0 = <&edp_hpd>;
> +&gpio0 {
> + gpio-line-names = "PMIC_SLEEP_AP",
> + "DDRIO_PWROFF",
> + "DDRIO_RETEN",
> + "TS3A227E_INT_L",
> + "PMIC_INT_L",
> + "PWR_KEY_L",
> + "AP_LID_INT_L",
> + "EC_IN_RW",
> +
> + "AC_PRESENT_AP",
> + /*
> + * RECOVERY_SW_L is Chrome OS ABI. Schematics call
> + * it REC_MODE_L.
> + */
> + "RECOVERY_SW_L",
> + "OTP_OUT",
> + "HOST1_PWR_EN",
> + "USBOTG_PWREN_H",
> + "AP_WARM_RESET_H",
> + "nFAULT2",
> + "I2C0_SDA_PMIC",
> +
> + "I2C0_SCL_PMIC",
> + "SUSPEND_L",
> + "USB_INT";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "CONFIG0",
> + "CONFIG1",
> + "CONFIG2",
> + "",
> + "",
> + "",
> + "",
> + "CONFIG3",
> +
> + "",
> + "EMMC_RST_L",
> + "",
> + "",
> + "BL_PWR_EN",
> + "AVDD_1V8_DISP_EN";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "FLASH0_D0",
> + "FLASH0_D1",
> + "FLASH0_D2",
> + "FLASH0_D3",
> + "FLASH0_D4",
> + "FLASH0_D5",
> + "FLASH0_D6",
> + "FLASH0_D7",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "FLASH0_CS2/EMMC_CMD",
> + "",
> + "FLASH0_DQS/EMMC_CLKO";
> +};
> +
> +&gpio4 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "UART0_RXD",
> + "UART0_TXD",
> + "UART0_CTS",
> + "UART0_RTS",
> + "SDIO0_D0",
> + "SDIO0_D1",
> + "SDIO0_D2",
> + "SDIO0_D3",
> +
> + "SDIO0_CMD",
> + "SDIO0_CLK",
> + "BT_DEV_WAKE",
> + "",
> + "WIFI_ENABLE_H",
> + "BT_ENABLE_L",
> + "WIFI_HOST_WAKE",
> + "BT_HOST_WAKE";
> +};
> +
> +&gpio5 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "SPI0_CLK",
> + "SPI0_CS0",
> + "SPI0_TXD",
> + "SPI0_RXD",
> +
> + "",
> + "",
> + "",
> + "VCC50_HDMI_EN";
> +};
> +
> +&gpio6 {
> + gpio-line-names = "I2S0_SCLK",
> + "I2S0_LRCK_RX",
> + "I2S0_LRCK_TX",
> + "I2S0_SDI",
> + "I2S0_SDO0",
> + "HP_DET_H",
> + "",
> + "INT_CODEC",
> +
> + "I2S0_CLK",
> + "I2C2_SDA",
> + "I2C2_SCL",
> + "MICDET",
> + "",
> + "",
> + "",
> + "",
> +
> + "SDMMC_D0",
> + "SDMMC_D1",
> + "SDMMC_D2",
> + "SDMMC_D3",
> + "SDMMC_CLK",
> + "SDMMC_CMD";
> +};
> +
> +&gpio7 {
> + gpio-line-names = "LCDC_BL",
> + "PWM_LOG",
> + "BL_EN",
> + "TRACKPAD_INT",
> + "TPM_INT_H",
> + "SDMMC_DET_L",
> + /*
> + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
> + * it FW_WP_AP.
> + */
> + "AP_FLASH_WP_L",
> + "EC_INT",
> +
> + "CPU_NMI",
> + "DVSOK",
> + "",
> + "EDP_HPD",
> + "DVS1",
> + "nFAULT1",
> + "LCD_EN",
> + "DVS2",
> +
> + "VCC5V_GOOD_H",
> + "I2C4_SDA_TP",
> + "I2C4_SCL_TP",
> + "I2C5_SDA_HDMI",
> + "I2C5_SCL_HDMI",
> + "5V_DRV",
> + "UART2_RXD",
> + "UART2_TXD";
> +};
> +
> +&gpio8 {
> + gpio-line-names = "RAM_ID0",
> + "RAM_ID1",
> + "RAM_ID2",
> + "RAM_ID3",
> + "I2C1_SDA_TPM",
> + "I2C1_SCL_TPM",
> + "SPI2_CLK",
> + "SPI2_CS0",
> +
> + "SPI2_RXD",
> + "SPI2_TXD";
> };
>
> &pinctrl {
> - backlight {
> - bl_pwr_en: bl_pwr_en {
> - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Wake only */
> + &suspend_l_wake
> + &bt_dev_wake_awake
> + >;
> + pinctrl-1 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Sleep only */
> + &suspend_l_sleep
> + &bt_dev_wake_sleep
> + >;
>
> buck-5v {
> drv_5v: drv-5v {
> - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - emmc {
> - /* Make sure eMMC is not in reset */
> - emmc_deassert_reset: emmc-deassert-reset {
> - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> hdmi {
> vcc50_hdmi_en: vcc50-hdmi-en {
> - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - lcd {
> - lcd_enable_h: lcd-en {
> - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> -
> - avdd_1v8_disp_en: avdd-1v8-disp-en {
> - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> pmic {
> dvs_1: dvs-1 {
> - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
> };
>
> dvs_2: dvs-2 {
> - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
> };
> };
> };
> @@ -182,24 +474,18 @@
> pinctrl-0 = <&i2c4_xfer &trackpad_int>;
>
> trackpad@15 {
> - compatible = "elan,i2c_touchpad";
> - interrupt-parent = <&gpio7>;
> - interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> /*
> * Remove the inherited pinctrl settings to avoid clashing
> * with bus-wide ones.
> */
> /delete-property/pinctrl-names;
> /delete-property/pinctrl-0;
> - reg = <0x15>;
> - vcc-supply = <&vcc33_io>;
> - wakeup-source;
> };
>
> trackpad@2c {
> compatible = "hid-over-i2c";
> interrupt-parent = <&gpio7>;
> - interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> + interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
> reg = <0x2c>;
> hid-descr-addr = <0x0020>;
> vcc-supply = <&vcc33_io>;
> diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
> index 0521d9e0..ffd1121d 100644
> --- a/arch/arm/dts/rk3288-veyron-mickey.dts
> +++ b/arch/arm/dts/rk3288-veyron-mickey.dts
> @@ -1,49 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Google Veyron Mickey Rev 0 board device tree source
> *
> * Copyright 2015 Google, Inc
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> /dts-v1/;
> -#include "rk3288-veyron-chromebook.dtsi"
> +#include "rk3288-veyron.dtsi"
> +#include "rk3288-veyron-broadcom-bluetooth.dtsi"
>
> / {
> model = "Google Mickey";
> @@ -65,6 +29,13 @@
> regulator-boot-on;
> vin-supply = <&vcc33_sys>;
> };
> +
> + sound {
> + compatible = "rockchip,rockchip-audio-max98090";
> + rockchip,model = "VEYRON-HDMI";
> + rockchip,hdmi-codec = <&hdmi>;
> + rockchip,i2s-controller = <&i2s>;
> + };
> };
>
> &cpu_thermal {
> @@ -112,14 +83,18 @@
> cooling-maps {
> /*
> * After 1st level, throttle the CPU down to as low as 1.4 GHz
> - * and don't let the GPU go faster than 400 MHz. Note that we
> - * won't throttle the GPU lower than 400 MHz due to CPU
> - * heat--we'll let the GPU do the rest itself.
> + * and don't let the GPU go faster than 400 MHz.
> */
> cpu_warm_limit_cpu {
> trip = <&cpu_alert_warm>;
> - cooling-device =
> - <&cpu0 THERMAL_NO_LIMIT 4>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
> + <&cpu1 THERMAL_NO_LIMIT 4>,
> + <&cpu2 THERMAL_NO_LIMIT 4>,
> + <&cpu3 THERMAL_NO_LIMIT 4>;
> + };
> + cpu_warm_limit_gpu {
> + trip = <&cpu_alert_warm>;
> + cooling-device = <&gpu 1 1>;
> };
>
> /*
> @@ -140,29 +115,100 @@
> */
> cpu_almost_hot_limit_cpu {
> trip = <&cpu_alert_almost_hot>;
> - cooling-device =
> - <&cpu0 5 6>;
> + cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
> + <&cpu3 5 6>;
> };
> cpu_hot_limit_cpu {
> trip = <&cpu_alert_hot>;
> - cooling-device =
> - <&cpu0 7 7>;
> + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
> + <&cpu3 7 7>;
> };
> cpu_hotter_limit_cpu {
> trip = <&cpu_alert_hotter>;
> - cooling-device =
> - <&cpu0 7 8>;
> + cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
> + <&cpu3 7 8>;
> };
> cpu_very_hot_limit_cpu {
> trip = <&cpu_alert_very_hot>;
> - cooling-device =
> - <&cpu0 8 THERMAL_NO_LIMIT>;
> + cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>,
> + <&cpu1 8 THERMAL_NO_LIMIT>,
> + <&cpu2 8 THERMAL_NO_LIMIT>,
> + <&cpu3 8 THERMAL_NO_LIMIT>;
> + };
> +
> + /* At very hot, don't let GPU go over 300 MHz */
> + cpu_very_hot_limit_gpu {
> + trip = <&cpu_alert_very_hot>;
> + cooling-device = <&gpu 2 2>;
> };
> };
> };
>
> -&emmc {
> - /delete-property/mmc-hs200-1_8v;
> +&gpu_thermal {
> + /delete-node/ trips;
> + /delete-node/ cooling-maps;
> +
> + trips {
> + gpu_alert_warmish: gpu_alert_warmish {
> + temperature = <60000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + gpu_alert_warm: gpu_alert_warm {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + gpu_alert_hotter: gpu_alert_hotter {
> + temperature = <84000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + gpu_alert_very_very_hot: gpu_alert_very_very_hot {
> + temperature = <86000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + gpu_crit: gpu_crit {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + /* After 1st level throttle the GPU down to as low as 400 MHz */
> + gpu_warmish_limit_gpu {
> + trip = <&gpu_alert_warmish>;
> + cooling-device = <&gpu THERMAL_NO_LIMIT 1>;
> + };
> +
> + /*
> + * Slightly after we throttle the GPU, we'll also make sure that
> + * the CPU can't go faster than 1.4 GHz. Note that we won't
> + * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll
> + * let the CPU do the rest itself.
> + */
> + gpu_warm_limit_cpu {
> + trip = <&gpu_alert_warm>;
> + cooling-device = <&cpu0 4 4>,
> + <&cpu1 4 4>,
> + <&cpu2 4 4>,
> + <&cpu3 4 4>;
> + };
> +
> + /* When hot, GPU goes down to 300 MHz */
> + gpu_hotter_limit_gpu {
> + trip = <&gpu_alert_hotter>;
> + cooling-device = <&gpu 2 2>;
> + };
> +
> + /* When really hot, don't let GPU go _above_ 300 MHz */
> + gpu_very_very_hot_limit_gpu {
> + trip = <&gpu_alert_very_very_hot>;
> + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> &i2c2 {
> @@ -175,15 +221,13 @@
>
> &i2s {
> status = "okay";
> - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
> - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
> };
>
> &rk808 {
> pinctrl-names = "default";
> pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
> - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
> - <&gpio7 15 GPIO_ACTIVE_HIGH>;
> + dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
> + <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
>
> /delete-property/ vcc6-supply;
> /delete-property/ vcc12-supply;
> @@ -216,40 +260,183 @@
> };
> };
>
> +&gpio0 {
> + gpio-line-names = "PMIC_SLEEP_AP",
> + "",
> + "",
> + "",
> + "PMIC_INT_L",
> + "POWER_BUTTON_L",
> + "",
> + "",
> +
> + "",
> + /*
> + * RECOVERY_SW_L is Chrome OS ABI. Schematics call
> + * it REC_MODE_L.
> + */
> + "RECOVERY_SW_L",
> + "OT_RESET",
> + "",
> + "",
> + "AP_WARM_RESET_H",
> + "",
> + "I2C0_SDA_PMIC",
> +
> + "I2C0_SCL_PMIC",
> + "",
> + "nFALUT";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "CONFIG0",
> + "CONFIG1",
> + "CONFIG2",
> + "",
> + "",
> + "",
> + "",
> + "CONFIG3",
> +
> + "",
> + "EMMC_RST_L";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "FLASH0_D0",
> + "FLASH0_D1",
> + "FLASH0_D2",
> + "FLASH0_D3",
> + "FLASH0_D4",
> + "FLASH0_D5",
> + "FLASH0_D6",
> + "FLASH0_D7",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "FLASH0_CS2/EMMC_CMD",
> + "",
> + "FLASH0_DQS/EMMC_CLKO";
> +};
> +
> +&gpio4 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "UART0_RXD",
> + "UART0_TXD",
> + "UART0_CTS_L",
> + "UART0_RTS_L",
> + "SDIO0_D0",
> + "SDIO0_D1",
> + "SDIO0_D2",
> + "SDIO0_D3",
> +
> + "SDIO0_CMD",
> + "SDIO0_CLK",
> + "BT_DEV_WAKE",
> + "",
> + "WIFI_ENABLE_H",
> + "BT_ENABLE_L",
> + "WIFI_HOST_WAKE",
> + "BT_HOST_WAKE";
> +};
> +
> +&gpio7 {
> + gpio-line-names = "",
> + "PWM_LOG",
> + "",
> + "",
> + "TPM_INT_H",
> + "SDMMC_DET_L",
> + /*
> + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
> + * it FW_WP_AP.
> + */
> + "AP_FLASH_WP_L",
> + "",
> +
> + "CPU_NMI",
> + "DVSOK",
> + "HDMI_WAKE",
> + "POWER_HDMI_ON",
> + "DVS1",
> + "",
> + "",
> + "DVS2",
> +
> + "HDMI_CEC",
> + "",
> + "",
> + "I2C5_SDA_HDMI",
> + "I2C5_SCL_HDMI",
> + "",
> + "UART2_RXD",
> + "UART2_TXD";
> +};
> +
> +&gpio8 {
> + gpio-line-names = "RAM_ID0",
> + "RAM_ID1",
> + "RAM_ID2",
> + "RAM_ID3",
> + "I2C1_SDA_TPM",
> + "I2C1_SCL_TPM",
> + "SPI2_CLK",
> + "SPI2_CS0",
> +
> + "SPI2_RXD",
> + "SPI2_TXD";
> +};
> +
> &pinctrl {
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> + >;
> +
> hdmi {
> power_hdmi_on: power-hdmi-on {
> - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> pmic {
> dvs_1: dvs-1 {
> - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
> };
>
> dvs_2: dvs-2 {
> - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
> };
> };
> };
>
> -&sdmmc {
> - status = "disabled";
> -};
> -
> -&sdio0 {
> - status = "disabled";
> -};
> -
> -&sdmmc {
> - status = "disabled";
> -};
> -
> -&spi0 {
> - status = "disabled";
> -};
> -
> &usb_host0_ehci {
> status = "disabled";
> };
> @@ -260,7 +447,7 @@
>
> &vcc50_hdmi {
> enable-active-high;
> - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&power_hdmi_on>;
> };
> diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts
> index b56a3f4f..82fc6fba 100644
> --- a/arch/arm/dts/rk3288-veyron-minnie.dts
> +++ b/arch/arm/dts/rk3288-veyron-minnie.dts
> @@ -1,49 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Google Veyron Minnie Rev 0+ board device tree source
> *
> * Copyright 2015 Google, Inc
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> /dts-v1/;
> #include "rk3288-veyron-chromebook.dtsi"
> +#include "rk3288-veyron-broadcom-bluetooth.dtsi"
>
> / {
> model = "Google Minnie";
> @@ -52,111 +16,31 @@
> "google,veyron-minnie-rev0", "google,veyron-minnie",
> "google,veyron", "rockchip,rk3288";
>
> - backlight_regulator: backlight-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&bl_pwr_en>;
> - regulator-name = "backlight_regulator";
> - vin-supply = <&vcc33_sys>;
> - startup-delay-us = <15000>;
> - };
> -
> - panel_regulator: panel-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&lcd_enable_h>;
> - regulator-name = "panel_regulator";
> - startup-delay-us = <100000>;
> - vin-supply = <&vcc33_sys>;
> - };
> -
> - vcc18_lcd: vcc18-lcd {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
> + volume_buttons: volume-buttons {
> + compatible = "gpio-keys";
> pinctrl-names = "default";
> - pinctrl-0 = <&avdd_1v8_disp_en>;
> - regulator-name = "vcc18_lcd";
> - regulator-always-on;
> - regulator-boot-on;
> - vin-supply = <&vcc18_wl>;
> - };
> -
> - sound {
> - compatible = "rockchip,audio-max98090-jerry";
> + pinctrl-0 = <&volum_down_l &volum_up_l>;
>
> - cpu {
> - sound-dai = <&i2s 0>;
> + volum_down {
> + label = "Volum_down";
> + gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + debounce-interval = <100>;
> };
>
> - codec {
> - sound-dai = <&max98090 0>;
> + volum_up {
> + label = "Volum_up";
> + gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + debounce-interval = <100>;
> };
> };
> };
>
> &backlight {
> /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
> - brightness-levels = <
> - 0 3 4 5 6 7
> - 8 9 10 11 12 13 14 15
> - 16 17 18 19 20 21 22 23
> - 24 25 26 27 28 29 30 31
> - 32 33 34 35 36 37 38 39
> - 40 41 42 43 44 45 46 47
> - 48 49 50 51 52 53 54 55
> - 56 57 58 59 60 61 62 63
> - 64 65 66 67 68 69 70 71
> - 72 73 74 75 76 77 78 79
> - 80 81 82 83 84 85 86 87
> - 88 89 90 91 92 93 94 95
> - 96 97 98 99 100 101 102 103
> - 104 105 106 107 108 109 110 111
> - 112 113 114 115 116 117 118 119
> - 120 121 122 123 124 125 126 127
> - 128 129 130 131 132 133 134 135
> - 136 137 138 139 140 141 142 143
> - 144 145 146 147 148 149 150 151
> - 152 153 154 155 156 157 158 159
> - 160 161 162 163 164 165 166 167
> - 168 169 170 171 172 173 174 175
> - 176 177 178 179 180 181 182 183
> - 184 185 186 187 188 189 190 191
> - 192 193 194 195 196 197 198 199
> - 200 201 202 203 204 205 206 207
> - 208 209 210 211 212 213 214 215
> - 216 217 218 219 220 221 222 223
> - 224 225 226 227 228 229 230 231
> - 232 233 234 235 236 237 238 239
> - 240 241 242 243 244 245 246 247
> - 248 249 250 251 252 253 254 255>;
> - power-supply = <&backlight_regulator>;
> -};
> -
> -&emmc {
> - /delete-property/mmc-hs200-1_8v;
> -};
> -
> -&gpio_keys {
> - pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>;
> -
> - volum_down {
> - label = "Volum_down";
> - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEDOWN>;
> - debounce-interval = <100>;
> - };
> -
> - volum_up {
> - label = "Volum_up";
> - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEUP>;
> - debounce-interval = <100>;
> - };
> + brightness-levels = <3 255>;
> + num-interpolated-steps = <252>;
> };
>
> &i2c_tunnel {
> @@ -177,18 +61,31 @@
> compatible = "elan,ekth3500";
> reg = <0x10>;
> interrupt-parent = <&gpio2>;
> - interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
> + interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
> pinctrl-names = "default";
> pinctrl-0 = <&touch_int &touch_rst>;
> - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
> + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
> vcc33-supply = <&vcc33_touch>;
> vccio-supply = <&vcc33_touch>;
> };
> };
>
> &panel {
> - compatible = "auo,b101ean01", "simple-panel";
> - power-supply= <&panel_regulator>;
> + compatible = "auo,b101ean01";
> +
> + /delete-node/ panel-timing;
> +
> + panel-timing {
> + clock-frequency = <66666667>;
> + hactive = <1280>;
> + hfront-porch = <18>;
> + hback-porch = <21>;
> + hsync-len = <32>;
> + vactive = <800>;
> + vfront-porch = <4>;
> + vback-porch = <8>;
> + vsync-len = <18>;
> + };
> };
>
> &rk808 {
> @@ -217,86 +114,302 @@
> &sdmmc {
> disable-wp;
> pinctrl-names = "default";
> - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
> &sdmmc_bus4>;
> };
>
> &vcc_5v {
> enable-active-high;
> - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&drv_5v>;
> };
>
> &vcc50_hdmi {
> enable-active-high;
> - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
> + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&vcc50_hdmi_en>;
> };
>
> +&gpio0 {
> + gpio-line-names = "PMIC_SLEEP_AP",
> + "DDRIO_PWROFF",
> + "DDRIO_RETEN",
> + "TS3A227E_INT_L",
> + "PMIC_INT_L",
> + "PWR_KEY_L",
> + "AP_LID_INT_L",
> + "EC_IN_RW",
> +
> + "AC_PRESENT_AP",
> + /*
> + * RECOVERY_SW_L is Chrome OS ABI. Schematics call
> + * it REC_MODE_L.
> + */
> + "RECOVERY_SW_L",
> + "OTP_OUT",
> + "HOST1_PWR_EN",
> + "USBOTG_PWREN_H",
> + "AP_WARM_RESET_H",
> + "nFALUT2",
> + "I2C0_SDA_PMIC",
> +
> + "I2C0_SCL_PMIC",
> + "SUSPEND_L",
> + "USB_INT";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "CONFIG0",
> + "CONFIG1",
> + "CONFIG2",
> + "",
> + "",
> + "",
> + "",
> + "CONFIG3",
> +
> + "PROCHOT#",
> + "EMMC_RST_L",
> + "",
> + "",
> + "BL_PWR_EN",
> + "AVDD_1V8_DISP_EN",
> + "TOUCH_INT",
> + "TOUCH_RST",
> +
> + "I2C3_SCL_TP",
> + "I2C3_SDA_TP";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "FLASH0_D0",
> + "FLASH0_D1",
> + "FLASH0_D2",
> + "FLASH0_D3",
> + "FLASH0_D4",
> + "FLASH0_D5",
> + "FLASH0_D6",
> + "FLASH0_D7",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "FLASH0_CS2/EMMC_CMD",
> + "",
> + "FLASH0_DQS/EMMC_CLKO";
> +};
> +
> +&gpio4 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "UART0_RXD",
> + "UART0_TXD",
> + "UART0_CTS",
> + "UART0_RTS",
> + "SDIO0_D0",
> + "SDIO0_D1",
> + "SDIO0_D2",
> + "SDIO0_D3",
> +
> + "SDIO0_CMD",
> + "SDIO0_CLK",
> + "dev_wake",
> + "",
> + "WIFI_ENABLE_H",
> + "BT_ENABLE_L",
> + "WIFI_HOST_WAKE",
> + "BT_HOST_WAKE";
> +};
> +
> +&gpio5 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "Volum_Up#",
> + "Volum_Down#",
> + "SPI0_CLK",
> + "SPI0_CS0",
> + "SPI0_TXD",
> + "SPI0_RXD",
> +
> + "",
> + "",
> + "",
> + "VCC50_HDMI_EN";
> +};
> +
> +&gpio6 {
> + gpio-line-names = "I2S0_SCLK",
> + "I2S0_LRCK_RX",
> + "I2S0_LRCK_TX",
> + "I2S0_SDI",
> + "I2S0_SDO0",
> + "HP_DET_H",
> + "",
> + "INT_CODEC",
> +
> + "I2S0_CLK",
> + "I2C2_SDA",
> + "I2C2_SCL",
> + "MICDET",
> + "",
> + "",
> + "",
> + "",
> +
> + "SDMMC_D0",
> + "SDMMC_D1",
> + "SDMMC_D2",
> + "SDMMC_D3",
> + "SDMMC_CLK",
> + "SDMMC_CMD";
> +};
> +
> +&gpio7 {
> + gpio-line-names = "LCDC_BL",
> + "PWM_LOG",
> + "BL_EN",
> + "TRACKPAD_INT",
> + "TPM_INT_H",
> + "SDMMC_DET_L",
> + /*
> + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
> + * it FW_WP_AP.
> + */
> + "AP_FLASH_WP_L",
> + "EC_INT",
> +
> + "CPU_NMI",
> + "DVS_OK",
> + "SDMMC_WP",
> + "EDP_HPD",
> + "DVS1",
> + "nFALUT1",
> + "LCD_EN",
> + "DVS2",
> +
> + "VCC5V_GOOD_H",
> + "I2C4_SDA_TP",
> + "I2C4_SCL_TP",
> + "I2C5_SDA_HDMI",
> + "I2C5_SCL_HDMI",
> + "5V_DRV",
> + "UART2_RXD",
> + "UART2_TXD";
> +};
> +
> +&gpio8 {
> + gpio-line-names = "RAM_ID0",
> + "RAM_ID1",
> + "RAM_ID2",
> + "RAM_ID3",
> + "I2C1_SDA_TPM",
> + "I2C1_SCL_TPM",
> + "SPI2_CLK",
> + "SPI2_CS0",
> +
> + "SPI2_RXD",
> + "SPI2_TXD";
> +};
> +
> &pinctrl {
> - backlight {
> - bl_pwr_en: bl_pwr_en {
> - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Wake only */
> + &suspend_l_wake
> + >;
> + pinctrl-1 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Sleep only */
> + &suspend_l_sleep
> + >;
>
> buck-5v {
> drv_5v: drv-5v {
> - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> buttons {
> volum_down_l: volum-down-l {
> - rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
> };
>
> volum_up_l: volum-up-l {
> - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> hdmi {
> vcc50_hdmi_en: vcc50-hdmi-en {
> - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - lcd {
> - lcd_enable_h: lcd-en {
> - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> -
> - avdd_1v8_disp_en: avdd-1v8-disp-en {
> - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> pmic {
> dvs_1: dvs-1 {
> - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
> };
>
> dvs_2: dvs-2 {
> - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
> };
> };
>
> prochot {
> gpio_prochot: gpio-prochot {
> - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> touchscreen {
> touch_int: touch-int {
> - rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> };
>
> touch_rst: touch-rst {
> - rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
> };
> diff --git a/arch/arm/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/dts/rk3288-veyron-sdmmc.dtsi
> new file mode 100644
> index 00000000..27fb06ce
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-sdmmc.dtsi
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Veyron (and derivatives) fragment for sdmmc cards
> + *
> + * Copyright 2015 Google, Inc
> + */
> +
> +&io_domains {
> + sdcard-supply = <&vccio_sd>;
> +};
> +
> +&pinctrl {
> + sdmmc {
> + /*
> + * We run sdmmc at max speed; bump up drive strength.
> + * We also have external pulls, so disable the internal ones.
> + */
> + sdmmc_bus4: sdmmc-bus4 {
> + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
> + <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
> + <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
> + <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
> + };
> +
> + sdmmc_clk: sdmmc-clk {
> + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
> + };
> +
> + sdmmc_cmd: sdmmc-cmd {
> + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
> + };
> +
> + /*
> + * Builtin CD line is hooked to ground to prevent JTAG at boot
> + * (and also to get the voltage rail correct).
> + * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
> + * think there's a card inserted
> + */
> + sdmmc_cd_disabled: sdmmc-cd-disabled {
> + rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + /* This is where we actually hook up CD */
> + sdmmc_cd_pin: sdmmc-cd-pin {
> + rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&rk808 {
> + vcc9-supply = <&vcc_5v>;
> +
> + regulators {
> + vccio_sd: LDO_REG4 {
> + regulator-name = "vccio_sd";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc33_sd: LDO_REG5 {
> + regulator-name = "vcc33_sd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> + };
> +};
> +
> +&sdmmc {
> + status = "okay";
> +
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
> + rockchip,default-sample-phase = <90>;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc33_sd>;
> + vqmmc-supply = <&vccio_sd>;
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts
> index 58c1fe96..4a3ea934 100644
> --- a/arch/arm/dts/rk3288-veyron-speedy.dts
> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
> @@ -7,8 +7,8 @@
>
> /dts-v1/;
> #include "rk3288-veyron-chromebook.dtsi"
> +#include "rk3288-veyron-broadcom-bluetooth.dtsi"
> #include "cros-ec-sbs.dtsi"
> -#include "rk3288-veyron-speedy-u-boot.dtsi"
>
> / {
> model = "Google Speedy";
> @@ -17,44 +17,6 @@
> "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> -
> - panel_regulator: panel-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&lcd_enable_h>;
> - regulator-name = "panel_regulator";
> - startup-delay-us = <100000>;
> - vin-supply = <&vcc33_sys>;
> - };
> -
> - vcc18_lcd: vcc18-lcd {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&avdd_1v8_disp_en>;
> - regulator-name = "vcc18_lcd";
> - regulator-always-on;
> - regulator-boot-on;
> - vin-supply = <&vcc18_wl>;
> - };
> -
> - backlight_regulator: backlight-regulator {
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&bl_pwr_en>;
> - regulator-name = "backlight_regulator";
> - vin-supply = <&vcc33_sys>;
> - startup-delay-us = <15000>;
> - };
> -};
> -
> -&backlight {
> - power-supply = <&backlight_regulator>;
> };
>
> &cpu_alert0 {
> @@ -65,6 +27,10 @@
> temperature = <70000>;
> };
>
> +&cpu_crit {
> + temperature = <90000>;
> +};
> +
> &edp {
> /delete-property/pinctrl-names;
> /delete-property/pinctrl-0;
> @@ -72,8 +38,12 @@
> force-hpd;
> };
>
> -&panel {
> - power-supply = <&panel_regulator>;
> +&gpu_alert0 {
> + temperature = <80000>;
> +};
> +
> +&gpu_crit {
> + temperature = <90000>;
> };
>
> &rk808 {
> @@ -84,7 +54,7 @@
> &sdmmc {
> disable-wp;
> pinctrl-names = "default";
> - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
> &sdmmc_bus4>;
> };
>
> @@ -102,42 +72,253 @@
> pinctrl-0 = <&vcc50_hdmi_en>;
> };
>
> +&gpio0 {
> + gpio-line-names = "PMIC_SLEEP_AP",
> + "DDRIO_PWROFF",
> + "DDRIO_RETEN",
> + "TS3A227E_INT_L",
> + "PMIC_INT_L",
> + "PWR_KEY_L",
> + "AP_LID_INT_L",
> + "EC_IN_RW",
> +
> + "AC_PRESENT_AP",
> + /*
> + * RECOVERY_SW_L is Chrome OS ABI. Schematics call
> + * it REC_MODE_L.
> + */
> + "RECOVERY_SW_L",
> + "OTP_OUT",
> + "HOST1_PWR_EN",
> + "USBOTG_PWREN_H",
> + "AP_WARM_RESET_H",
> + "nFALUT2",
> + "I2C0_SDA_PMIC",
> +
> + "I2C0_SCL_PMIC",
> + "SUSPEND_L",
> + "USB_INT";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "CONFIG0",
> + "CONFIG1",
> + "CONFIG2",
> + "",
> + "",
> + "",
> + "",
> + "CONFIG3",
> +
> + "PWRLIMIT#_CPU",
> + "EMMC_RST_L",
> + "",
> + "",
> + "BL_PWR_EN",
> + "AVDD_1V8_DISP_EN";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "FLASH0_D0",
> + "FLASH0_D1",
> + "FLASH0_D2",
> + "FLASH0_D3",
> + "FLASH0_D4",
> + "FLASH0_D5",
> + "FLASH0_D6",
> + "FLASH0_D7",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "FLASH0_CS2/EMMC_CMD",
> + "",
> + "FLASH0_DQS/EMMC_CLKO";
> +};
> +
> +&gpio4 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "UART0_RXD",
> + "UART0_TXD",
> + "UART0_CTS",
> + "UART0_RTS",
> + "SDIO0_D0",
> + "SDIO0_D1",
> + "SDIO0_D2",
> + "SDIO0_D3",
> +
> + "SDIO0_CMD",
> + "SDIO0_CLK",
> + "BT_DEV_WAKE",
> + "",
> + "WIFI_ENABLE_H",
> + "BT_ENABLE_L",
> + "WIFI_HOST_WAKE",
> + "BT_HOST_WAKE";
> +};
> +
> +&gpio5 {
> + gpio-line-names = "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> + "",
> +
> + "",
> + "",
> + "",
> + "",
> + "SPI0_CLK",
> + "SPI0_CS0",
> + "SPI0_TXD",
> + "SPI0_RXD",
> +
> + "",
> + "",
> + "",
> + "VCC50_HDMI_EN";
> +};
> +
> +&gpio6 {
> + gpio-line-names = "I2S0_SCLK",
> + "I2S0_LRCK_RX",
> + "I2S0_LRCK_TX",
> + "I2S0_SDI",
> + "I2S0_SDO0",
> + "HP_DET_H",
> + "ALS_INT", /* not connected */
> + "INT_CODEC",
> +
> + "I2S0_CLK",
> + "I2C2_SDA",
> + "I2C2_SCL",
> + "MICDET",
> + "",
> + "",
> + "",
> + "",
> +
> + "SDMMC_D0",
> + "SDMMC_D1",
> + "SDMMC_D2",
> + "SDMMC_D3",
> + "SDMMC_CLK",
> + "SDMMC_CMD";
> +};
> +
> +&gpio7 {
> + gpio-line-names = "LCDC_BL",
> + "PWM_LOG",
> + "BL_EN",
> + "TRACKPAD_INT",
> + "TPM_INT_H",
> + "SDMMC_DET_L",
> + /*
> + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
> + * it FW_WP_AP.
> + */
> + "AP_FLASH_WP_L",
> + "EC_INT",
> +
> + "CPU_NMI",
> + "DVS_OK",
> + "",
> + "EDP_HOTPLUG",
> + "DVS1",
> + "nFALUT1",
> + "LCD_EN",
> + "DVS2",
> +
> + "VCC5V_GOOD_H",
> + "I2C4_SDA_TP",
> + "I2C4_SCL_TP",
> + "I2C5_SDA_HDMI",
> + "I2C5_SCL_HDMI",
> + "5V_DRV",
> + "UART2_RXD",
> + "UART2_TXD";
> +};
> +
> +&gpio8 {
> + gpio-line-names = "RAM_ID0",
> + "RAM_ID1",
> + "RAM_ID2",
> + "RAM_ID3",
> + "I2C1_SDA_TPM",
> + "I2C1_SCL_TPM",
> + "SPI2_CLK",
> + "SPI2_CS0",
> +
> + "SPI2_RXD",
> + "SPI2_TXD";
> +};
> +
> &pinctrl {
> - backlight {
> - bl_pwr_en: bl_pwr_en {
> - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Wake only */
> + &suspend_l_wake
> + >;
> + pinctrl-1 = <
> + /* Common for sleep and wake, but no owners */
> + &ddr0_retention
> + &ddrio_pwroff
> + &global_pwroff
> +
> + /* Sleep only */
> + &suspend_l_sleep
> + >;
>
> buck-5v {
> drv_5v: drv-5v {
> - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> hdmi {
> vcc50_hdmi_en: vcc50-hdmi-en {
> - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - lcd {
> - lcd_enable_h: lcd-en {
> - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> -
> - avdd_1v8_disp_en: avdd-1v8-disp-en {
> - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> pmic {
> dvs_1: dvs-1 {
> - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
> };
>
> dvs_2: dvs-2 {
> - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
> };
> };
> };
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index ac9e815e..2b7dc2c5 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -1,8 +1,8 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Google Veyron (and derivatives) board device tree source
> *
> - * Copyright 2014 Google, Inc
> + * Copyright 2015 Google, Inc
> */
>
> #include <dt-bindings/clock/rockchip,rk808.h>
> @@ -10,150 +10,83 @@
> #include "rk3288.dtsi"
>
> / {
> - memory {
> - reg = <0x0 0x80000000>;
> - };
> -
> chosen {
> - stdout-path = &uart2;
> + stdout-path = "serial2:115200n8";
> };
>
> - firmware {
> - chromeos {
> - pinctrl-names = "default";
> - pinctrl-0 = <&fw_wp_ap>;
> - write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
> - };
> - };
> -
> - backlight: backlight {
> - compatible = "pwm-backlight";
> - brightness-levels = <
> - 0 1 2 3 4 5 6 7
> - 8 9 10 11 12 13 14 15
> - 16 17 18 19 20 21 22 23
> - 24 25 26 27 28 29 30 31
> - 32 33 34 35 36 37 38 39
> - 40 41 42 43 44 45 46 47
> - 48 49 50 51 52 53 54 55
> - 56 57 58 59 60 61 62 63
> - 64 65 66 67 68 69 70 71
> - 72 73 74 75 76 77 78 79
> - 80 81 82 83 84 85 86 87
> - 88 89 90 91 92 93 94 95
> - 96 97 98 99 100 101 102 103
> - 104 105 106 107 108 109 110 111
> - 112 113 114 115 116 117 118 119
> - 120 121 122 123 124 125 126 127
> - 128 129 130 131 132 133 134 135
> - 136 137 138 139 140 141 142 143
> - 144 145 146 147 148 149 150 151
> - 152 153 154 155 156 157 158 159
> - 160 161 162 163 164 165 166 167
> - 168 169 170 171 172 173 174 175
> - 176 177 178 179 180 181 182 183
> - 184 185 186 187 188 189 190 191
> - 192 193 194 195 196 197 198 199
> - 200 201 202 203 204 205 206 207
> - 208 209 210 211 212 213 214 215
> - 216 217 218 219 220 221 222 223
> - 224 225 226 227 228 229 230 231
> - 232 233 234 235 236 237 238 239
> - 240 241 242 243 244 245 246 247
> - 248 249 250 251 252 253 254 255>;
> - default-brightness-level = <128>;
> - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
> - backlight-boot-off;
> - pinctrl-names = "default";
> - pinctrl-0 = <&bl_en>;
> - pwms = <&pwm0 0 1000000 0>;
> + /*
> + * The default coreboot on veyron devices ignores memory@0 nodes
> + * and would instead create another memory node.
> + */
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x80000000>;
> };
>
> - panel: panel {
> - compatible ="cnm,n116bgeea2","simple-panel";
> - status = "okay";
> - power-supply = <&vcc33_lcd>;
> - backlight = <&backlight>;
> - };
>
> - gpio_keys: gpio-keys {
> + power_button: power-button {
> compatible = "gpio-keys";
> -
> pinctrl-names = "default";
> - pinctrl-0 = <&pwr_key_h>;
> + pinctrl-0 = <&pwr_key_l>;
> +
> power {
> label = "Power";
> - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
> + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
> linux,code = <KEY_POWER>;
> debounce-interval = <100>;
> - gpio-key,wakeup;
> + wakeup-source;
> };
> };
>
> gpio-restart {
> compatible = "gpio-restart";
> - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
> + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&ap_warm_reset_h>;
> - priority = /bits/ 8 <200>;
> + priority = <200>;
> };
>
> emmc_pwrseq: emmc-pwrseq {
> compatible = "mmc-pwrseq-emmc";
> pinctrl-0 = <&emmc_reset>;
> pinctrl-names = "default";
> - reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
> };
>
> - sound {
> - compatible = "rockchip,rockchip-audio-max98090";
> - rockchip,model = "ROCKCHIP-I2S";
> - rockchip,i2s-controller = <&i2s>;
> - rockchip,audio-codec = <&max98090>;
> - rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
> - rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
> - rockchip,headset-codec = <&headsetcodec>;
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&rk808 RK808_CLKOUT1>;
> + clock-names = "ext_clock";
> pinctrl-names = "default";
> - pinctrl-0 = <&mic_det>, <&hp_det>;
> - };
> -
> - vdd_logic: pwm-regulator {
> - compatible = "pwm-regulator";
> - pwms = <&pwm1 0 2000 0>;
> -
> - voltage-table = <1350000 0>,
> - <1300000 10>,
> - <1250000 20>,
> - <1200000 31>,
> - <1150000 41>,
> - <1100000 52>,
> - <1050000 62>,
> - <1000000 72>,
> - < 950000 83>;
> + pinctrl-0 = <&wifi_enable_h>;
>
> - regulator-min-microvolt = <950000>;
> - regulator-max-microvolt = <1350000>;
> - regulator-name = "vdd_logic";
> - regulator-ramp-delay = <4000>;
> + /*
> + * Depending on the actual card populated GPIO4 D4
> + * correspond to one of these signals on the module:
> + *
> + * D4:
> + * - SDIO_RESET_L_WL_REG_ON
> + * - PDN (power down when low)
> + */
> + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
> };
>
> - vcc33_sys: vcc33-sys {
> + vcc_5v: vcc-5v {
> compatible = "regulator-fixed";
> - regulator-name = "vcc33_sys";
> + regulator-name = "vcc_5v";
> regulator-always-on;
> regulator-boot-on;
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - vin-supply = <&vccsys>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> };
>
> - vcc_5v: vcc-5v {
> + vcc33_sys: vcc33-sys {
> compatible = "regulator-fixed";
> - regulator-name = "vcc_5v";
> + regulator-name = "vcc33_sys";
> regulator-always-on;
> regulator-boot-on;
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> };
>
> vcc50_hdmi: vcc50-hdmi {
> @@ -164,39 +97,21 @@
> vin-supply = <&vcc_5v>;
> };
>
> - bt_regulator: bt-regulator {
> - /*
> - * On the module itself this is one of these (depending
> - * on the actual card pouplated):
> - * - BT_I2S_WS_BT_RFDISABLE_L
> - * - No connect
> - */
> -
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&bt_enable_l>;
> - regulator-name = "bt_regulator";
> - };
> + vdd_logic: vdd-logic {
> + compatible = "pwm-regulator";
> + regulator-name = "vdd_logic";
>
> - wifi_regulator: wifi-regulator {
> - /*
> - * On the module itself this is one of these (depending
> - * on the actual card populated):
> - * - SDIO_RESET_L_WL_REG_ON
> - * - PDN (power down when low)
> - */
> + pwms = <&pwm1 0 1994 0>;
> + pwm-supply = <&vcc33_sys>;
>
> - compatible = "regulator-fixed";
> - enable-active-high;
> - gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&wifi_enable_h>;
> - regulator-name = "wifi_regulator";
> + pwm-dutycycle-range = <0x7b 0>;
> + pwm-dutycycle-unit = <0x94>;
>
> - /* Faux input supply. See bt_regulator description. */
> - vin-supply = <&bt_regulator>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <4000>;
> };
> };
>
> @@ -204,71 +119,62 @@
> cpu0-supply = <&vdd_cpu>;
> };
>
> -&efuse {
> - status = "okay";
> +&cpu_crit {
> + temperature = <100000>;
> +};
> +
> +/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
> +&cpu_opp_table {
> + /delete-node/ opp-312000000;
> +
> + opp-1512000000 {
> + opp-microvolt = <1250000>;
> + };
> + opp-1608000000 {
> + opp-microvolt = <1300000>;
> + };
> + opp-1704000000 {
> + opp-hz = /bits/ 64 <1704000000>;
> + opp-microvolt = <1350000>;
> + };
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1400000>;
> + };
> };
>
> &emmc {
> - broken-cd;
> + status = "okay";
> +
> bus-width = <8>;
> cap-mmc-highspeed;
> + rockchip,default-sample-phase = <158>;
> + disable-wp;
> mmc-hs200-1_8v;
> mmc-pwrseq = <&emmc_pwrseq>;
> - disable-wp;
> non-removable;
> - num-slots = <1>;
> pinctrl-names = "default";
> - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
> - status = "okay";
> + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
> };
>
> -&sdio0 {
> - broken-cd;
> - bus-width = <4>;
> - cap-sd-highspeed;
> - sd-uhs-sdr12;
> - sd-uhs-sdr25;
> - sd-uhs-sdr50;
> - sd-uhs-sdr104;
> - cap-sdio-irq;
> - card-external-vcc-supply = <&wifi_regulator>;
> - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
> - <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
> - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
> - keep-power-in-suspend;
> - non-removable;
> - num-slots = <1>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
> +&gpu {
> + mali-supply = <&vdd_gpu>;
> status = "okay";
> - vmmc-supply = <&vcc33_sys>;
> - vqmmc-supply = <&vcc18_wl>;
> };
>
> -&sdmmc {
> - bus-width = <4>;
> - cap-mmc-highspeed;
> - cap-sd-highspeed;
> - sd-uhs-sdr12;
> - sd-uhs-sdr25;
> - sd-uhs-sdr50;
> - sd-uhs-sdr104;
> - card-detect-delay = <200>;
> - cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
> - num-slots = <1>;
> - status = "okay";
> - vmmc-supply = <&vcc33_sd>;
> - vqmmc-supply = <&vccio_sd>;
> +&gpu_alert0 {
> + temperature = <72500>;
> };
>
> -&spi2 {
> - status = "okay";
> +&gpu_crit {
> + temperature = <100000>;
> +};
>
> - spi_flash: spiflash@0 {
> - compatible = "spidev", "jedec,spi-nor";
> - spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
> - reg = <0>;
> - };
> +&hdmi {
> + pinctrl-names = "default", "unwedge";
> + pinctrl-0 = <&hdmi_ddc>;
> + pinctrl-1 = <&hdmi_ddc_unwedge>;
> + status = "okay";
> };
>
> &i2c0 {
> @@ -280,12 +186,12 @@
>
> rk808: pmic@1b {
> compatible = "rockchip,rk808";
> + reg = <0x1b>;
> clock-output-names = "xin32k", "wifibt_32kin";
> interrupt-parent = <&gpio0>;
> - interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
> + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
> pinctrl-names = "default";
> pinctrl-0 = <&pmic_int_l>;
> - reg = <0x1b>;
> rockchip,system-power-controller;
> wakeup-source;
> #clock-cells = <1>;
> @@ -297,39 +203,41 @@
> vcc6-supply = <&vcc_5v>;
> vcc7-supply = <&vcc33_sys>;
> vcc8-supply = <&vcc33_sys>;
> - vcc9-supply = <&vcc_5v>;
> - vcc10-supply = <&vcc33_sys>;
> - vcc11-supply = <&vcc_5v>;
> vcc12-supply = <&vcc_18>;
> -
> vddio-supply = <&vcc33_io>;
>
> regulators {
> vdd_cpu: DCDC_REG1 {
> + regulator-name = "vdd_arm";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <750000>;
> regulator-max-microvolt = <1450000>;
> - regulator-name = "vdd_arm";
> regulator-ramp-delay = <6001>;
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
>
> vdd_gpu: DCDC_REG2 {
> + regulator-name = "vdd_gpu";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <1250000>;
> - regulator-name = "vdd_gpu";
> regulator-ramp-delay = <6001>;
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
>
> vcc135_ddr: DCDC_REG3 {
> + regulator-name = "vcc135_ddr";
> regulator-always-on;
> regulator-boot-on;
> - regulator-name = "vcc135_ddr";
> - regulator-suspend-mem-enabled;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> };
>
> /*
> @@ -340,12 +248,15 @@
> * power measurement purposes).
> */
> vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
> + regulator-name = "vcc_18";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <1800000>;
> regulator-max-microvolt = <1800000>;
> - regulator-name = "vcc_18";
> - regulator-suspend-mem-microvolt = <1800000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> };
>
> /*
> @@ -356,60 +267,47 @@
> * (such as danger) they're the same net.
> */
> vcc33_io: LDO_REG1 {
> + regulator-name = "vcc33_io";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> - regulator-name = "vcc33_io";
> - regulator-suspend-mem-microvolt = <3300000>;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> };
>
> vdd_10: LDO_REG3 {
> + regulator-name = "vdd_10";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <1000000>;
> regulator-max-microvolt = <1000000>;
> - regulator-name = "vdd_10";
> - regulator-suspend-mem-microvolt = <1000000>;
> - };
> -
> - vccio_sd: LDO_REG4 {
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-name = "vccio_sd";
> - regulator-suspend-mem-disabled;
> - };
> -
> - vcc33_sd: LDO_REG5 {
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-name = "vcc33_sd";
> - regulator-suspend-mem-disabled;
> - };
> -
> - vcc18_codec: LDO_REG6 {
> - regulator-always-on;
> - regulator-boot-on;
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-name = "vcc18_codec";
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> };
>
> vdd10_lcd_pwren_h: LDO_REG7 {
> + regulator-name = "vdd10_lcd_pwren_h";
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <2500000>;
> regulator-max-microvolt = <2500000>;
> - regulator-name = "vdd10_lcd_pwren_h";
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
>
> vcc33_lcd: SWITCH_REG1 {
> + regulator-name = "vcc33_lcd";
> regulator-always-on;
> regulator-boot-on;
> - regulator-name = "vcc33_lcd";
> - regulator-suspend-mem-disabled;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> };
> };
> };
> @@ -436,24 +334,6 @@
> clock-frequency = <100000>;
> i2c-scl-falling-time-ns = <50>; /* 10ns measured */
> i2c-scl-rising-time-ns = <800>; /* 600ns measured */
> -
> - max98090: max98090@10 {
> - compatible = "maxim,max98090";
> - reg = <0x10>;
> - #sound-dai-cells = <0>;
> - interrupt-parent = <&gpio6>;
> - interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&int_codec>;
> - };
> -};
> -
> -&i2c3 {
> - status = "okay";
> -
> - clock-frequency = <400000>;
> - i2c-scl-falling-time-ns = <50>;
> - i2c-scl-rising-time-ns = <300>;
> };
>
> &i2c4 {
> @@ -462,56 +342,61 @@
> clock-frequency = <400000>;
> i2c-scl-falling-time-ns = <50>; /* 11ns measured */
> i2c-scl-rising-time-ns = <300>; /* 225ns measured */
> -
> - headsetcodec: ts3a227e@3b {
> - compatible = "ti,ts3a227e";
> - reg = <0x3b>;
> - interrupt-parent = <&gpio0>;
> - interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&ts3a227e_int_l>;
> - ti,micbias = <7>; /* MICBIAS = 2.8V */
> - };
> -};
> -
> -&i2c5 {
> - status = "okay";
> -
> - clock-frequency = <100000>;
> - i2c-scl-falling-time-ns = <300>;
> - i2c-scl-rising-time-ns = <1000>;
> -};
> -
> -&i2s {
> - status = "okay";
> - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
> - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
> };
>
> &io_domains {
> status = "okay";
>
> - audio-supply = <&vcc18_codec>;
> bb-supply = <&vcc33_io>;
> dvp-supply = <&vcc_18>;
> flash0-supply = <&vcc18_flashio>;
> gpio1830-supply = <&vcc33_io>;
> gpio30-supply = <&vcc33_io>;
> lcdc-supply = <&vcc33_lcd>;
> - sdcard-supply = <&vccio_sd>;
> wifi-supply = <&vcc18_wl>;
> };
>
> -&wdt {
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&sdio0 {
> status = "okay";
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc33_sys>;
> + vqmmc-supply = <&vcc18_wl>;
> };
>
> -&pwm0 {
> +&spi2 {
> status = "okay";
> +
> + rx-sample-delay-ns = <12>;
> +
> + spi_flash: flash@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + };
> };
>
> -&pwm1 {
> +&tsadc {
> status = "okay";
> +
> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
> + rockchip,hw-tshut-temp = <125000>;
> };
>
> &uart0 {
> @@ -520,9 +405,6 @@
> /* Pins don't include flow control by default; add that in */
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
> - /* We need to go faster than 24MHz, so adjust clock parents / rates */
> - assigned-clocks = <&cru SCLK_UART0>;
> - assigned-clock-rates = <48000000>;
> };
>
> &uart1 {
> @@ -531,67 +413,47 @@
>
> &uart2 {
> status = "okay";
> - reg-shift = <2>;
> };
>
> -&vopb {
> +&usbphy {
> status = "okay";
> };
>
> -&vopb_mmu {
> +&usb_host0_ehci {
> status = "okay";
> -};
>
> -&vopl {
> - status = "okay";
> + needs-reset-on-resume;
> };
>
> -&vopl_mmu {
> +&usb_host1 {
> status = "okay";
> + snps,need-phy-for-wake;
> };
>
> -&edp {
> +&usb_otg {
> status = "okay";
> - rockchip,panel = <&panel>;
> +
> + assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
> + assigned-clock-parents = <&usbphy0>;
> + dr_mode = "host";
> + snps,need-phy-for-wake;
> };
>
> -&hdmi {
> +&vopb {
> status = "okay";
> };
>
> -&gpu {
> +&vopb_mmu {
> status = "okay";
> };
>
> -&tsadc {
> - tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> - tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
> +&wdt {
> status = "okay";
> };
>
> &pinctrl {
> - pinctrl-names = "default", "sleep";
> - pinctrl-0 = <
> - /* Common for sleep and wake, but no owners */
> - &ddr0_retention
> - &ddrio_pwroff
> - &global_pwroff
> -
> - /* Wake only */
> - &bt_dev_wake_awake
> - >;
> - pinctrl-1 = <
> - /* Common for sleep and wake, but no owners */
> - &ddr0_retention
> - &ddrio_pwroff
> - &global_pwroff
> -
> - /* Sleep only */
> - &bt_dev_wake_sleep
> - >;
> -
> - /* Add this for sdmmc pins to SD card */
> pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
> + bias-disable;
> drive-strength = <8>;
> };
>
> @@ -608,33 +470,15 @@
> output-low;
> };
>
> - backlight {
> - bl_en: bl-en {
> - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> buttons {
> - pwr_key_h: pwr-key-h {
> - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
> - };
> - };
> -
> - codec {
> - hp_det: hp-det {
> - rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
> - };
> - int_codec: int-codec {
> - rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
> - };
> - mic_det: mic-det {
> - rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
> + pwr_key_l: pwr-key-l {
> + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> emmc {
> emmc_reset: emmc-reset {
> - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
> };
>
> /*
> @@ -642,54 +486,59 @@
> * We also have external pulls, so disable the internal ones.
> */
> emmc_clk: emmc-clk {
> - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
> + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
> };
>
> emmc_cmd: emmc-cmd {
> - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
> + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
> };
>
> emmc_bus8: emmc-bus8 {
> - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
> - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
> - };
> - };
> -
> - headset {
> - ts3a227e_int_l: ts3a227e-int-l {
> - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
> + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
> + <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
> };
> };
>
> pmic {
> pmic_int_l: pmic-int-l {
> - /*
> - * Causes jerry to hang when probing bus 0
> - * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
> - */
> + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> reboot {
> ap_warm_reset_h: ap-warm-reset-h {
> - rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + recovery-switch {
> + rec_mode_l: rec-mode-l {
> + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> sdio0 {
> wifi_enable_h: wifienable-h {
> - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
> };
>
> /* NOTE: mislabelled on schematic; should be bt_enable_h */
> bt_enable_l: bt-enable-l {
> - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + bt_host_wake: bt-host-wake {
> + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> +
> + bt_host_wake_l: bt-host-wake-l {
> + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
> };
>
> /*
> @@ -697,100 +546,48 @@
> * We also have external pulls, so disable the internal ones.
> */
> sdio0_bus4: sdio0-bus4 {
> - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
> + <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
> + <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
> + <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
> };
>
> sdio0_cmd: sdio0-cmd {
> - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
> };
>
> sdio0_clk: sdio0-clk {
> - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
> };
>
> /*
> * These pins are only present on very new veyron boards; on
> * older boards bt_dev_wake is simply always high. Note that
> - * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
> + * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
> * to map this pin everywhere
> */
> bt_dev_wake_sleep: bt-dev-wake-sleep {
> - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
> + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
> };
>
> bt_dev_wake_awake: bt-dev-wake-awake {
> - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
> - };
> - };
> -
> - sdmmc {
> - /*
> - * We run sdmmc at max speed; bump up drive strength.
> - * We also have external pulls, so disable the internal ones.
> - */
> - sdmmc_bus4: sdmmc-bus4 {
> - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
> - <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> - };
> -
> - sdmmc_clk: sdmmc-clk {
> - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> - };
> -
> - sdmmc_cmd: sdmmc-cmd {
> - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> - };
> -
> - /*
> - * Builtin CD line is hooked to ground to prevent JTAG at boot
> - * (and also to get the voltage rail correct). Make we
> - * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
> - * think there's a card inserted
> - */
> - sdmmc_cd_disabled: sdmmc-cd-disabled {
> - rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
> };
>
> - /* This is where we actually hook up CD */
> - sdmmc_cd_gpio: sdmmc-cd-gpio {
> - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
> + bt_dev_wake: bt-dev-wake {
> + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> tpm {
> tpm_int_h: tpm-int-h {
> - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> write-protect {
> fw_wp_ap: fw-wp-ap {
> - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
> };
> -
> -&usbphy {
> - status = "okay";
> -};
> -
> -&usb_host0_ehci {
> - status = "okay";
> - needs-reset-on-resume;
> -};
> -
> -&usb_host1 {
> - status = "okay";
> -};
> -
> -&usb_otg {
> - dr_mode = "host";
> - status = "okay";
> - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
> - assigned-clock-parents = <&cru SCLK_OTGPHY0>;
> -};