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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id b20-20020a376714000000b0067b21e5d18asm1075896qkc.105.2022.03.09.08.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 08:10:54 -0800 (PST) Date: Wed, 9 Mar 2022 11:10:52 -0500 From: Tom Rini To: haibo.chen@nxp.com, Jaehoon Chung , Peng Fan , Stefano Babic Cc: peng.fan@nxp.com, jh80.chung@samsung.com, festevam@gmail.com, sean.anderson@seco.com, u-boot@lists.denx.de, marex@denx.de, aford173@gmail.com, tharvey@gateworks.com, andrey.zhizhikin@leica-geosystems.com, uboot-imx@nxp.com Subject: Re: [PATCH v2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary Message-ID: <20220309161052.GA2128647@bill-the-cat> References: <1645500498-5500-1-git-send-email-haibo.chen@nxp.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="zYM0uCDKw75PZbzx" Content-Disposition: inline In-Reply-To: <1645500498-5500-1-git-send-email-haibo.chen@nxp.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean --zYM0uCDKw75PZbzx Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 22, 2022 at 11:28:18AM +0800, haibo.chen@nxp.com wrote: > From: Haibo Chen >=20 > After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use > VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it > involve issue in mmc_switch_voltage(), because of the special > design of usdhc. >=20 > For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, > these are reserved bits(Though RM contain the definition of these bits, > but actually internal IC logic do not implement, already confirm with > IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card > clock output. Here is the definition of this bit in RM: >=20 > [8] FRC_SDCLK_ON > Force CLK output active > Do not set this bit to 1 unless it is necessary. Also, make sure that > this bit is cleared when uSDHC=E2=80=99s clock is about to be changed (fr= equency > change, clock source change, or delay chain tuning). > 0b - CLK active or inactive is fully controlled by the hardware. > 1b - Force CLK active >=20 > In default, the FRC_SDCLK_ON is 0. This means, when there is no command > or data transfer on bus, hardware will gate off the card clock. But in > some case, we need the card clock keep on. Take IO voltage 1.8v switch > as example, after IO voltage change to 1.8v, spec require gate off the > card clock for 5ms, and gate on the clock back, once detect the card > clock on, then the card will draw the dat0 to high immediately. If there > is not clock gate off/on behavior, some card will keep the dat0 to low > level. This is the reason we fail in mmc_switch_voltage(). >=20 > To fix this issue, and concern that this is only the fsl usdhc hardware > design limitation, set the bit FRC_SDCLK_ON in the beginning of the > wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage > switch process align with SD specification. >=20 > For standard tuning process, usdhc specification also require the card > clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). >=20 > Reviewed-by: Marek Vasut > Tested-by: Fabio Estevam > Signed-off-by: Haibo Chen > Reviewed-by: Peng Fan > Reviewed-by: Jaehoon Chung > --- > drivers/mmc/fsl_esdhc_imx.c | 25 ++++++++++++++++++++++--- > include/fsl_esdhc_imx.h | 2 ++ > 2 files changed, 24 insertions(+), 3 deletions(-) Is this going to get picked up in the imx or mmc trees soon, or should I take this directly? Thanks! --=20 Tom --zYM0uCDKw75PZbzx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmIo0YMACgkQFHw5/5Y0 tyzXcAwAhJiYCwz05Pm1b1j5acEOa5sXoC0YNJflnGh4cGbpkhRieh6SkE1n71tW iqmbY+fvjZ7al0+pMRRtuhk/nMCZRa75gZBg6LxgFhBzxvjhXMQA/Qw7fV/DWyYG Si3WxvMVA2lP3JMJjTmdq1DjKd9xEOJ8lA1TkMJAE0Q2Rqkt1OT3+VjcfdqZ/iEw 0Hk7WbbrUf87ENawFDAzcWfoWVuBg/TK3GLw3N5c3Nn6wqXRfXvL4BtJ6h6m+3O+ W2/H8e3q1T7AQnvbDlkzHI0nUTnX4NJwfNXflc00TOPfYLXvFQ3/m44b5rIUOzCb 38ky1Q59o5ZvK1EQW1k2gs+fiE6i+77iSW4LfdcK5XBfz0Gaxtsj5DM+Mv8ZPbUB sNTDOrqCy/5saAKLnR5cpZtgd/XXHPyN+NMLpORMwV69x8LqaKpmOpRDVKyLHX9g F9/Xk1e35iyBr/ZmNbHeSQ+zKv7eFvcNIS4HCdTUkjL6xIGWbnh99kCkyzJzE0IN 2f3G3m8J =ZvgY -----END PGP SIGNATURE----- --zYM0uCDKw75PZbzx--