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From: Sam Shih <sam.shih@mediatek.com>
To: Tom Rini <trini@konsulko.com>, Ryder Lee <ryder.lee@mediatek.com>,
	Weijie Gao <weijie.gao@mediatek.com>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
	<u-boot@lists.denx.de>
Cc: Sam Shih <sam.shih@mediatek.com>
Subject: [0/3] Add support for different mediatek pinctrl designs
Date: Thu, 10 Mar 2022 12:31:42 +0800	[thread overview]
Message-ID: <20220310043145.7690-1-sam.shih@mediatek.com> (raw)

MediaTek SoC's pinconf register usage varies by SoC,
So the original code uses V0/V1 to mark different pinconf design.
But actually, the real difference is the design of the "pin" itself.

Different SoCs will choose specify "pin design", which we call the
"io_type" of the pin.

For a better understanding of mediatek pinctrl design. and make the
driver clear and flexible, this patch series changes common parts
of mediatek pinctrl driver to support various pinctrl controller
designs.


Sam Shih (3):
  pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
  pinctrl: mediatek: introduce multiple memory bases support
  pinctrl: mediatek: add support for different types of IO pins

 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 217 ++++++++++++++----
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  79 ++++++-
 2 files changed, 243 insertions(+), 53 deletions(-)

-- 
2.29.2


             reply	other threads:[~2022-03-10  4:33 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-10  4:31 Sam Shih [this message]
2022-03-10  4:31 ` [1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
2022-03-25 20:42   ` Tom Rini
2022-03-10  4:31 ` [2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
2022-03-10  4:31 ` [3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih

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