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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id x6-20020a05622a000600b002e1bd939657sm7236997qtw.70.2022.03.14.11.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 11:14:07 -0700 (PDT) Date: Mon, 14 Mar 2022 14:14:05 -0400 From: Tom Rini To: Alper Nebi Yasak Cc: u-boot@lists.denx.de, Jack Mitchell , Kever Yang , Heinrich Schuchardt , Yifeng Zhao , Samuel Dionne-Riel , Simon Glass , Aswath Govindraju , Philipp Tomsich , Ashok Reddy Soma , Stephen Carlson , Jaehoon Chung , Michal Simek , Faiz Abbas , Jagan Teki , Peng Fan , Peter Robinson Subject: Re: [PATCH v4 2/4] rockchip: sdhci: Fix RK3399 eMMC PHY power cycling Message-ID: <20220314181405.GF9986@bill-the-cat> References: <20220128224240.4226-1-alpernebiyasak@gmail.com> <20220128224240.4226-3-alpernebiyasak@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="TuBLotoxjxNtqonL" Content-Disposition: inline In-Reply-To: <20220128224240.4226-3-alpernebiyasak@gmail.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean --TuBLotoxjxNtqonL Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Jan 29, 2022 at 01:42:37AM +0300, Alper Nebi Yasak wrote: > The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its > clock speed to some higher speeds. This is dependent on the desired > SDHCI clock speed, and it looks like the PHY should be powered off while > setting the SDHCI clock in these cases. >=20 > Commit ac804143cfd1 ("mmc: rockchip_sdhci: add phy and clock config for > rk3399") attempts to do this in the set_ios_post() hook by setting the > SDHCI clock once more while the PHY is turned off/on as necessary, as > the SDHCI framework does not provide a way to override how it sets its > clock. However, the commit breaks reinitializing the eMMC on a few > boards including chromebook_kevin and reportedly ROCKPro64. >=20 > This patch reworks the power cycling to utilize the SDHCI framework > slightly better (using the set_control_reg() hook to power off the PHY > and set_ios_post() hook to power it back on) which happens to fix the > issue, at least on a chromebook_kevin. >=20 > Signed-off-by: Alper Nebi Yasak > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! --=20 Tom --TuBLotoxjxNtqonL Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmIvheoACgkQFHw5/5Y0 tywmiAv9FdPi6pOuB63tunpRNtXo4XTCLLbC2Idhh7VJKFZais06Jb4JREun3qMm 8A5UDJMB8eV3PuEZ520rxFtk/lC5IWJ/m1IhRLH2BzlDOGD70YgKakyG//TL7YWo uqYolRneTw81LV3gZ0G3FAmK23xmFVzWtbTYx9LxryZaHvSsBgdKMfZb+leJtx4H q+kQxbwX/9K4M4OD1YXimUqfylgngOt9B2KjMUe7leGGM7tVOgPYl6eY0cOStt+s fQzT2CP79XkKFLOm+kGyzu2HkubWTldjukF1ENfvQW033sZJcYOnIomhDNqGsupG 7R+b3PFR0FT3mzhGw4mYkrk+TaqjlVy+jL08hof0VM77pCbNy73bFXKYYkKeywNc ozV1fjLrom7g6tRdYhz9pzJbT6FdTSDexr+ZIgE9o8rIUkd+nouvzvlNvnJWMASp uQCJGNpWf/N8S82BdBB6T6zu420bn90PR8WYsBXTpuPc6iV/tCqezxYLljIg1Gv+ ouK+Y19N =TDEP -----END PGP SIGNATURE----- --TuBLotoxjxNtqonL--