From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5FA4C433F5 for ; Tue, 15 Mar 2022 09:41:29 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5DD7F83976; Tue, 15 Mar 2022 10:41:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 66204839AC; Tue, 15 Mar 2022 10:41:25 +0100 (CET) Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C2846838BF for ; Tue, 15 Mar 2022 10:41:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 22F9fF8l059073; Tue, 15 Mar 2022 17:41:15 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from atcfdc88 (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 15 Mar 2022 17:41:14 +0800 Date: Tue, 15 Mar 2022 17:41:11 +0800 From: Leo Liang To: Niklas Cassel CC: Sean Anderson , Rick Chen , "damien.lemoal@opensource.wdc.com" , "u-boot@lists.denx.de" Subject: Re: [PATCH v2 4/8] k210: dts: align plic node with Linux Message-ID: <20220315094111.GA28277@atcfdc88> References: <20220301103529.3060257-1-Niklas.Cassel@wdc.com> <20220301103529.3060257-5-Niklas.Cassel@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20220301103529.3060257-5-Niklas.Cassel@wdc.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 22F9fF8l059073 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tue, Mar 01, 2022 at 10:35:42AM +0000, Niklas Cassel wrote: > From: Niklas Cassel > > The Linux PLIC interrupt-controller driver actually initializes the hart > context registers in the PLIC driver exactly in the same order as > specified in the interrupts-extended device tree property. See the device > tree binding [1]. > > The ordering of the interrupts is therefore essential in order to > configure the PLIC correctly. > > Fix the order so that we will have sane IRQ behavior when booting Linux > with the u-boot device tree. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > Signed-off-by: Niklas Cassel Reviewed-by: Leo Yu-Chi Liang