From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B84E2C433F5 for ; Sat, 19 Mar 2022 12:23:15 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C968183990; Sat, 19 Mar 2022 13:23:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SDsnqlEp"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 661B18396A; Sat, 19 Mar 2022 13:23:10 +0100 (CET) Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 79C3B8366A for ; Sat, 19 Mar 2022 13:23:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=festevam@gmail.com Received: by mail-oo1-xc34.google.com with SMTP id y27-20020a4a9c1b000000b0032129651bb0so13539950ooj.2 for ; Sat, 19 Mar 2022 05:23:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dNfJrkHY/On84KgGB1xtqLm5PvGIyI/j9l0B8/jePOk=; b=SDsnqlEpZSjs8YJzuxFIVwE7x1L3lEcKmxoWfIoWtUxD9qq8waGmeXmSwfNtN7fQCY IaPqOTooNIgw/k8xQpzkntOQjY3mutrBVYV5Ut9sJaxi52B//SZRt6zqO4tLgEqfp8Cl fnn7JGLTgQCzs30DhPeG02aMrg3hi0l3g6TYhiGcHWdllRE9lARfxpfnR1AlEeXLHjNt +CH5+kCe393RA+mDLXbZZYoTVLnWDGzvD9awJPbVlmx1NBkNCf9/Bi1aGKmAuCe7uld2 qzCHr5QFbRREef/C9zirdtCB7VWuyUBSpL08SUhY0N80o9EwXUQEiOdKPkE/fI9wXBMh QraA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dNfJrkHY/On84KgGB1xtqLm5PvGIyI/j9l0B8/jePOk=; b=s2tndGRL9u9RJdmq7rzj87D4uT0v106pqadGMrTq4ZyMBLsoBvK6r8vfykSZKLCArc n/YodkWYwulxwvhF6TP3wgzpQE1+FF7k2YisQeie6eBQhDI6+cEAKB4E57aSYtFe26nQ VjzgD2f3ghoGc0e/1l+INGKzZA2xbbTzScnbFwTm9/V9Hctj/5rSfCgT09ElAoFWI14C QdoaSZwyXXFTthlfVNEOlTxd/KOAat6P1/7heOUNUo8wpWSFkqCg2svQhh890Ffe1kvW ezs8cYxyg1OSwN4fkk6P+hVHC70jRN0Qi10LU6yLsskVt2UPmi73zDoXTYgz8prFn1lx UT8g== X-Gm-Message-State: AOAM533PzfwRYuUeYIV6X5ROABVKzXqG/WtjdG6e2A1+yUnSoGLHxzUL vxHTXecfhXCdx/RQli14td4= X-Google-Smtp-Source: ABdhPJwdg1QYnZznnVRU0CY3AZ6jKnNQqRhITKEfvONS7QHZ/VvWvIwNkDiyYRg9OeR+n3Yc5KnzxQ== X-Received: by 2002:a05:6870:5b8c:b0:da:6a40:8e6e with SMTP id em12-20020a0568705b8c00b000da6a408e6emr8951783oab.177.1647692585001; Sat, 19 Mar 2022 05:23:05 -0700 (PDT) Received: from localhost.localdomain ([2804:431:d77e:806f:6364:2305:261c:c822]) by smtp.gmail.com with ESMTPSA id d2-20020a05683025c200b005c93d78e1f6sm5327983otu.29.2022.03.19.05.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Mar 2022 05:23:04 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Cc: paul.liu@linaro.org, u-boot@lists.denx.de, Fabio Estevam Subject: [PATCH 1/5] imx8mm-cl-iot-gate: Add SPL EEPROM support Date: Sat, 19 Mar 2022 09:22:45 -0300 Message-Id: <20220319122249.77456-1-festevam@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Fabio Estevam imx8mm-cl-iot-gate supports multiple DDR sizes and models. The DDR type can be retrieved from the EEPROM, so add SPL code that can be used to get the DDR information. Based on the original code from Compulab's U-Boot. Signed-off-by: Fabio Estevam --- board/compulab/imx8mm-cl-iot-gate/Makefile | 2 +- .../compulab/imx8mm-cl-iot-gate/eeprom_spl.c | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c diff --git a/board/compulab/imx8mm-cl-iot-gate/Makefile b/board/compulab/imx8mm-cl-iot-gate/Makefile index 3a2bfc4dc4b1..3800b21a6fd0 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Makefile +++ b/board/compulab/imx8mm-cl-iot-gate/Makefile @@ -8,6 +8,6 @@ obj-y += imx8mm-cl-iot-gate.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o eeprom_spl.o obj-y += ddr/ endif diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c new file mode 100644 index 000000000000..ee6d2bb0016a --- /dev/null +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* (C) Copyright 2019 CompuLab, Ltd. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +static iomux_v3_cfg_t const eeprom_pads[] = { + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13) + +static void cl_eeprom_we(int enable) +{ + static int done; + + if (done) { + gpio_direction_output(EEPROM_WP_GPIO, enable); + return; + } + + imx_iomux_v3_setup_multiple_pads(eeprom_pads, ARRAY_SIZE(eeprom_pads)); + gpio_request(EEPROM_WP_GPIO, "eeprom_wp"); + gpio_direction_output(EEPROM_WP_GPIO, enable); + done = 1; +} + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_read(dev, offset, buf, len); +} + +static int cl_eeprom_write(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + cl_eeprom_we(1); + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_write(dev, offset, buf, len); +} + +/* Reserved for fututre use area */ +#define BOARD_DDRINFO_OFFSET 0x40 +#define BOARD_DDR_SIZE 4 +static u32 board_ddrinfo = 0xdeadbeef; + +#define BOARD_DDRSUBIND_OFFSET 0x44 +#define BOARD_DDRSUBIND_SIZE 1 +static u8 board_ddrsubind = 0xff; + +#define BOARD_OSIZE_OFFSET 0x80 +#define BOARD_OSIZE_SIZE 4 +static u32 board_osize = 0xdeadbeef; + +#define BOARD_DDRINFO_VALID(A) ((A) != 0xdeadbeef) + +u32 cl_eeprom_get_ddrinfo(void) +{ + if (!BOARD_DDRINFO_VALID(board_ddrinfo)) { + if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDR_SIZE)) + return 0; + } + return board_ddrinfo; +}; + +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo) +{ + if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDR_SIZE)) + return 0; + + board_ddrinfo = ddrinfo; + + return board_ddrinfo; +}; + +u8 cl_eeprom_get_subind(void) +{ + if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + return board_ddrsubind; +}; + +u8 cl_eeprom_set_subind(u8 ddrsubind) +{ + if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + board_ddrsubind = ddrsubind; + + return board_ddrsubind; +}; + +/* override-size ifaces */ +u32 cl_eeprom_get_osize(void) +{ + if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE)) + return 0; + + return board_osize; +}; +#endif -- 2.25.1