From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55E9AC433EF for ; Sat, 19 Mar 2022 12:23:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AA5228395B; Sat, 19 Mar 2022 13:23:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P5K6oVfm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9622283AE2; Sat, 19 Mar 2022 13:23:14 +0100 (CET) Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D09F783921 for ; Sat, 19 Mar 2022 13:23:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=festevam@gmail.com Received: by mail-ot1-x32e.google.com with SMTP id x8-20020a9d6288000000b005b22c373759so7337152otk.8 for ; Sat, 19 Mar 2022 05:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=di3ExQqxm+QPv3O1eASqZJnyNuY8cUta8xu8d5KBsn8=; b=P5K6oVfmH7UpDruh8X2mpcTqCfEl3NRhmFnUISeLfhuw8ccIEYOp4ZL89lHHrmo+ij BQyA62M4zocxdT28gReNiXABn1rYI1yjUGulLFroh5J5grdIsIVmYk5ozmTY0illFUi9 NG1yY2+brGjuMzdYUjFyW+bY+smjhr3WIOtUAmMcxtBO++flgQES5NDnorAB5a6b15Yt U7sUFApdICfX3oD5fS0Pa+XTD1UlfJ/WT6jsuwHNvFd+Qf7zcHeD30m9ZeUiae+5GOze CmK5bRvWWhr7liJ8TZntV7YFkM5uwSB+3bpnC+3tqG6kWKfLPH6kVm6n5cIql/SdDQEc cPHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=di3ExQqxm+QPv3O1eASqZJnyNuY8cUta8xu8d5KBsn8=; b=FS8gI1KgEN7HVAsWRvWg+rAwrGo1U0ohIXnqRuzWoegGdO09HJ0GsNWvUgKLe4I3ZZ kumMICowfRRlYn7eg1rfz7kGlFJZ7S3pcDYvDDe0rqRpCvGC8HTuVwEbBHbfLNnYU6Mw LN4lXYy4d88pqvQFlsmF3RLtxHMpdU7ccUbkcnPHnKqEwmf32T6KnVCNZtg6B8wNS6Sp HiL3pBkSeOVlP0ePla3XvZf7TeJq2Fr9249azJVe0Dnq7NnayVHEMT6P63RuLyCaNJe+ +8NYvj5vcKMesWzwQl7j73e7BK5UcctCQdfsfzCrGwLV5Rlefa5a9kpFaVwSeQhGLMyF ctsw== X-Gm-Message-State: AOAM530Lcy6ZnxdicZ+QLpMQNliiTI4b90XxI88goQ1PkKQWvqxRIviD zVoJ1/nU60tiptsM3yIxMMI= X-Google-Smtp-Source: ABdhPJy5yrHYx5FAXQ13gCeKtcHrupKZ4LqmdxG6fMVLF5yDTgAU6DIP5UVZHVG57PYbPFjoYoac8g== X-Received: by 2002:a05:6830:23b6:b0:5b2:4ac0:9130 with SMTP id m22-20020a05683023b600b005b24ac09130mr4776720ots.196.1647692587526; Sat, 19 Mar 2022 05:23:07 -0700 (PDT) Received: from localhost.localdomain ([2804:431:d77e:806f:6364:2305:261c:c822]) by smtp.gmail.com with ESMTPSA id d2-20020a05683025c200b005c93d78e1f6sm5327983otu.29.2022.03.19.05.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Mar 2022 05:23:06 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Cc: paul.liu@linaro.org, u-boot@lists.denx.de, Fabio Estevam Subject: [PATCH 2/5] imx8mm-cl-iot-gate: Retrieve the DDR type from EEPROM Date: Sat, 19 Mar 2022 09:22:46 -0300 Message-Id: <20220319122249.77456-2-festevam@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220319122249.77456-1-festevam@gmail.com> References: <20220319122249.77456-1-festevam@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Fabio Estevam Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types. This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience: U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022 Improve the boot time by retrieving the correct DDR information from the EEPROM: U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022 Based on the original code from Compulab's U-Boot. Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM. Signed-off-by: Fabio Estevam --- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++--- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 5 +++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 42dd0dbf18fa..5b93491923e9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -22,6 +22,8 @@ #include #include "ddr.h" +#include + static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) { unsigned int tmp; @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void) (struct lpddr4_tcm_desc *)SPL_TCM_DATA; if (lpddr4_tcm_desc->sign != DEFAULT) { - /* if not in tcm scan mode */ + /* get ddr type from the eeprom if not in tcm scan mode */ + ddr_info = cl_eeprom_get_ddrinfo(); for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) { if (lpddr4_array[i].id == ddr_info && - lpddr4_array[i].subind == 0xff) { + lpddr4_array[i].subind == cl_eeprom_get_subind()) { ddr_found = 1; break; } @@ -198,10 +201,25 @@ void spl_dram_init_compulab(void) SPL_TCM_FINI; + if (ddr_found == 0) { + /* Update eeprom */ + cl_eeprom_set_ddrinfo(ddr_info_mrr); + mdelay(10); + ddr_info = cl_eeprom_get_ddrinfo(); + mdelay(10); + cl_eeprom_set_subind(lpddr4_array[i].subind); + /* make sure that the ddr_info has reached the eeprom */ + printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info); + if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) { + printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n"); + printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n"); + } + } + /* Pass the dram size to th U-Boot through the tcm memory */ { /* To figure out what to store into the TCM buffer */ /* For debug purpouse only. To override the real memsize */ - unsigned int ddr_tcm_size = 0; + unsigned int ddr_tcm_size = cl_eeprom_get_osize(); if (ddr_tcm_size == 0 || ddr_tcm_size == -1) ddr_tcm_size = lpddr4_array[i].size; diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h index 59c18911592e..f7d4fdc1016a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc { unsigned int count; }; +u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +u32 cl_eeprom_get_osize(void); #endif -- 2.25.1