From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBC2DC433EF for ; Tue, 22 Mar 2022 10:55:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2AAC88395F; Tue, 22 Mar 2022 11:55:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9B7EC839FD; Tue, 22 Mar 2022 11:55:19 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id E47228395F for ; Tue, 22 Mar 2022 11:55:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2FDF8106F; Tue, 22 Mar 2022 03:55:14 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DAC263F66F; Tue, 22 Mar 2022 03:55:11 -0700 (PDT) Date: Tue, 22 Mar 2022 10:54:19 +0000 From: Andre Przywara To: Jim Liu Cc: sr@denx.de, priyanka.jain@nxp.com, sjg@chromium.org, samuel@sholland.org, xypron.glpk@gmx.de, JJLIU0@nuvoton.com, michael@walle.cc, rasmus.villemoes@prevas.dk, judge.packham@gmail.com, pali@kernel.org, kettenis@openbsd.org, KWLIU@nuvoton.com, YSCHU@nuvoton.com, sven@svenpeter.dev, u-boot@lists.denx.de Subject: Re: [PATCH v7] wdt: nuvoton: Add support for Nuvoton Message-ID: <20220322105419.57e737d5@slackpad.lan> In-Reply-To: <20220322091953.22701-1-JJLIU0@nuvoton.com> References: <20220322091953.22701-1-JJLIU0@nuvoton.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tue, 22 Mar 2022 17:19:53 +0800 Jim Liu wrote: Hi, > Add watchdog controller driver for NPCM7xx/npcm8xx So this is now the same as v4, with both compatible strings listed. Which *might* be right, but my question still stands: Is the 845 watchdog compatible to the 740 version? Does the current Linux driver work? If yes (and your driver suggests so, because you treat the two compatible strings the same), then you would not need to list both *in the driver*, but just do so in the .dts file. So the driver just matches "nuvoton,npcm750-wdt" (as does the Linux driver), the nuvoton-common-npcm7xx.dtsi stays the same, but in the npcm845.dtsi you write: watchdog: watchdog@xxx { compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; interrupts = ... ... }; This way you don't need to change the (Linux) driver, and get away with one compatible string, for both devices. So can you please confirm that both are compatible. I couldn't find any information on that. Please just don't send another patch without answering the question ;-) Cheers, Andre > Signed-off-by: Jim Liu > Reviewed-by: Stefan Roese > Reviewed-by: Simon Glass > > Changes for v2: > - coding style cleanup > - change register type from struct > Changes for v3: > - remove common.h > Changes for v4: > - add a bit of detail about the device in Kconfig > - lower-case hex change > - remove the reset function delay. > Actually when setting writel(NPCM_WTR )the watchdog is resetting > the BMC > changes for v5: > - modify compatible name to support all NPCM SOC > changes for v6: > - followed linux kernel to modify compatible name > change for v7: > - add second compatible name to driver > --- > drivers/watchdog/Kconfig | 8 +++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/npcm_wdt.c | 117 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 126 insertions(+) > create mode 100644 drivers/watchdog/npcm_wdt.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index f90f0ca02b..d33882fb6a 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -196,6 +196,14 @@ config WDT_MTK > The watchdog timer is stopped when initialized. > It performs full SoC reset. > > +config WDT_NPCM > + bool "Nuvoton watchdog timer support" > + depends on WDT && ARCH_NPCM > + help > + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, > + The watchdog timer is stopped when initialized. > + It performs full SoC reset. > + > config WDT_OCTEONTX > bool "OcteonTX core watchdog support" > depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index a35bd559f5..1089cd21f5 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o > obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o > obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o > obj-$(CONFIG_WDT_MTK) += mtk_wdt.o > +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o > obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o > obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o > obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o > diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c > new file mode 100644 > index 0000000000..0aedb2fbe7 > --- /dev/null > +++ b/drivers/watchdog/npcm_wdt.c > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2022 Nuvoton Technology, Inc > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ > +#define NPCM_WTE BIT(7) /* Enable */ > +#define NPCM_WTIE BIT(6) /* Enable irq */ > +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ > +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ > +#define NPCM_WTRF BIT(2) /* Reset flag */ > +#define NPCM_WTRE BIT(1) /* Reset enable */ > +#define NPCM_WTR BIT(0) /* Reset counter */ > + > +struct npcm_wdt_priv { > + void __iomem *regs; > +}; > + > +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) > +{ > + struct npcm_wdt_priv *priv = dev_get_priv(dev); > + u32 time_out, val; > + > + time_out = (u32)(timeout_ms) / 1000; > + if (time_out < 2) > + val = 0x800; > + else if (time_out < 3) > + val = 0x420; > + else if (time_out < 6) > + val = 0x810; > + else if (time_out < 11) > + val = 0x430; > + else if (time_out < 22) > + val = 0x820; > + else if (time_out < 44) > + val = 0xc00; > + else if (time_out < 87) > + val = 0x830; > + else if (time_out < 173) > + val = 0xc10; > + else if (time_out < 688) > + val = 0xc20; > + else > + val = 0xc30; > + > + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; > + writel(val, priv->regs); > + > + return 0; > +} > + > +static int npcm_wdt_stop(struct udevice *dev) > +{ > + struct npcm_wdt_priv *priv = dev_get_priv(dev); > + > + writel(0, priv->regs); > + > + return 0; > +} > + > +static int npcm_wdt_reset(struct udevice *dev) > +{ > + struct npcm_wdt_priv *priv = dev_get_priv(dev); > + > + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); > + > + return 0; > +} > + > +static int npcm_wdt_of_to_plat(struct udevice *dev) > +{ > + struct npcm_wdt_priv *priv = dev_get_priv(dev); > + > + priv->regs = dev_read_addr_ptr(dev); > + if (!priv->regs) > + return -EINVAL; > + > + return 0; > +} > + > +static const struct wdt_ops npcm_wdt_ops = { > + .start = npcm_wdt_start, > + .reset = npcm_wdt_reset, > + .stop = npcm_wdt_stop, > +}; > + > +static const struct udevice_id npcm_wdt_ids[] = { > + { .compatible = "nuvoton,npcm750-wdt" }, > + { .compatible = "nuvoton,npcm845-wdt" }, > + { } > +}; > + > +static int npcm_wdt_probe(struct udevice *dev) > +{ > + debug("%s() wdt%u\n", __func__, dev_seq(dev)); > + npcm_wdt_stop(dev); > + > + return 0; > +} > + > +U_BOOT_DRIVER(npcm_wdt) = { > + .name = "npcm_wdt", > + .id = UCLASS_WDT, > + .of_match = npcm_wdt_ids, > + .probe = npcm_wdt_probe, > + .priv_auto = sizeof(struct npcm_wdt_priv), > + .of_to_plat = npcm_wdt_of_to_plat, > + .ops = &npcm_wdt_ops, > +};