From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F8F3C433EF for ; Wed, 30 Mar 2022 10:11:03 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5808D8410D; Wed, 30 Mar 2022 12:09:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648634993; bh=yvCNC1U9zjeNowzT9t6cNO3O3z1a0GOMfElDCOmNvmI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jFUBBrgxMn53gfZQA8uVTV+w/scvlE2i1MFyuYexvYrak6aglALf4gYGA5iXonCEI hhrhK0JwZWw2IZGZlaeiPPvZyinCRL0GWP+p8cS/RYmXzb7vynslNzMPsen3kdDn7r qDVt+bm9JjhVjEt+XkUNIL78GcW/mFhPKlyG/tvhR4yvi+50EWgSeU64Hx33SpkUqO NaLvaYcEx8GA9SctNOZzl1DllzIk9gNzdBtHso2Pn0dnpo9L3QHGTvIan82KDBHxO0 PE+UkdnwnLV8vYjkObX5SjHjksyEFDWYmoZ7I8Lk5d0+jqPivks2UQnPAHnUD3Sn1V sQby6U0lh6yyw== Received: by phobos.denx.de (Postfix, from userid 109) id E4ADF840C5; Wed, 30 Mar 2022 12:08:27 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9E7EA840EA for ; Wed, 30 Mar 2022 12:07:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (unknown [91.198.250.119]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4KT2Df72KHz9sSb; Wed, 30 Mar 2022 12:07:46 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH 15/52] mips: octeon: Add cvmx-helper-loop.c Date: Wed, 30 Mar 2022 12:06:51 +0200 Message-Id: <20220330100728.871561-16-sr@denx.de> In-Reply-To: <20220330100728.871561-1-sr@denx.de> References: <20220330100728.871561-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-helper-loop.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/cvmx-helper-loop.c | 178 +++++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-helper-loop.c diff --git a/arch/mips/mach-octeon/cvmx-helper-loop.c b/arch/mips/mach-octeon/cvmx-helper-loop.c new file mode 100644 index 000000000000..8eaeac387df4 --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-helper-loop.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * Functions for LOOP initialization, configuration, + * and monitoring. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +int __cvmx_helper_loop_enumerate(int xiface) +{ + return OCTEON_IS_MODEL(OCTEON_CN68XX) ? + 8 : (OCTEON_IS_MODEL(OCTEON_CNF71XX) ? 2 : 4); +} + +/** + * @INTERNAL + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down + * after this call. + * + * @param xiface Interface to probe + * + * @return Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_loop_probe(int xiface) +{ + return __cvmx_helper_loop_enumerate(xiface); +} + +/** + * @INTERNAL + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @param interface to bring up + * + * @return Zero on success, negative on failure + */ +int __cvmx_helper_loop_enable(int xiface) +{ + cvmx_pip_prt_cfgx_t port_cfg; + int num_ports, index; + unsigned long offset; + struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface); + + num_ports = __cvmx_helper_get_num_ipd_ports(xiface); + /* + * We need to disable length checking so packet < 64 bytes and jumbo + * frames don't get errors + */ + for (index = 0; index < num_ports; index++) { + offset = ((octeon_has_feature(OCTEON_FEATURE_PKND)) ? + cvmx_helper_get_pknd(xiface, index) : + cvmx_helper_get_ipd_port(xiface, index)); + + if (octeon_has_feature(OCTEON_FEATURE_PKI)) { + cvmx_pki_endis_l2_errs(xi.node, offset, 1, 0, 0); + cvmx_pki_endis_fcs_check(xi.node, offset, 0, 0); + } else { + port_cfg.u64 = csr_rd(CVMX_PIP_PRT_CFGX(offset)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + csr_wr(CVMX_PIP_PRT_CFGX(offset), port_cfg.u64); + } + } + + /* + * Disable FCS stripping for loopback ports + */ + if (!octeon_has_feature(OCTEON_FEATURE_PKND)) { + cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs; + + ipd_sub_port_fcs.u64 = csr_rd(CVMX_IPD_SUB_PORT_FCS); + ipd_sub_port_fcs.s.port_bit2 = 0; + csr_wr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); + } + /* + * Set PKND and BPID for loopback ports. + */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { + cvmx_pko_reg_loopback_pkind_t lp_pknd; + cvmx_pko_reg_loopback_bpid_t lp_bpid; + + for (index = 0; index < num_ports; index++) { + int pknd = cvmx_helper_get_pknd(xiface, index); + int bpid = cvmx_helper_get_bpid(xiface, index); + + lp_pknd.u64 = csr_rd(CVMX_PKO_REG_LOOPBACK_PKIND); + lp_bpid.u64 = csr_rd(CVMX_PKO_REG_LOOPBACK_BPID); + + if (index == 0) + lp_pknd.s.num_ports = num_ports; + + switch (index) { + case 0: + lp_pknd.s.pkind0 = pknd; + lp_bpid.s.bpid0 = bpid; + break; + case 1: + lp_pknd.s.pkind1 = pknd; + lp_bpid.s.bpid1 = bpid; + break; + case 2: + lp_pknd.s.pkind2 = pknd; + lp_bpid.s.bpid2 = bpid; + break; + case 3: + lp_pknd.s.pkind3 = pknd; + lp_bpid.s.bpid3 = bpid; + break; + case 4: + lp_pknd.s.pkind4 = pknd; + lp_bpid.s.bpid4 = bpid; + break; + case 5: + lp_pknd.s.pkind5 = pknd; + lp_bpid.s.bpid5 = bpid; + break; + case 6: + lp_pknd.s.pkind6 = pknd; + lp_bpid.s.bpid6 = bpid; + break; + case 7: + lp_pknd.s.pkind7 = pknd; + lp_bpid.s.bpid7 = bpid; + break; + } + csr_wr(CVMX_PKO_REG_LOOPBACK_PKIND, lp_pknd.u64); + csr_wr(CVMX_PKO_REG_LOOPBACK_BPID, lp_bpid.u64); + } + } else if (octeon_has_feature(OCTEON_FEATURE_BGX)) { + cvmx_lbk_chx_pkind_t lbk_pkind; + + for (index = 0; index < num_ports; index++) { + lbk_pkind.u64 = 0; + lbk_pkind.s.pkind = cvmx_helper_get_pknd(xiface, index); + csr_wr_node(xi.node, CVMX_LBK_CHX_PKIND(index), + lbk_pkind.u64); + } + } + + return 0; +} -- 2.35.1