From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5793CC433F5 for ; Wed, 30 Mar 2022 10:17:35 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 43AE88419E; Wed, 30 Mar 2022 12:12:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648635175; bh=AXyFLUmoCtX7XZeRcxr06FRuRQXUkg1xbn0034lAVys=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=dIkKVcT/w2VXw6uEWwsxO2Qn4D4U1v2IYAAH6+9aiWtEfNYWhSGsu7ldE2TEl8ORy 7rsCoFkCGd18kLuJVTza5Iw+GyRaf1gY2+Tz6CVp8qhaLDaQAQHD6SUgwh4sa/elDl dcDe9l2H314VTFimqjzlvK+m4HqCPFYMgJ21A1hKLoM0OlDA94GpVIAK30cZNlCzpo 7F/0UNA03FhbUINBZRe9J84mwB9XsXdKCPerKTh3MLsnsbVPwCLdyh3DzUEinMG9OK Sfl/gXfARtlEfslks0ZKyEaKnnsCBCO8hJS/XVuI1o/oq6aHSEesdc1GGATqPTYYPP wujazn53t080A== Received: by phobos.denx.de (Postfix, from userid 109) id C7DFD840C1; Wed, 30 Mar 2022 12:09:26 +0200 (CEST) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7D273840CA for ; Wed, 30 Mar 2022 12:08:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (unknown [91.198.250.119]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4KT2F50H4Hz9sRG; Wed, 30 Mar 2022 12:08:09 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH 38/52] mips: octeon: Add cvmx-pko3-resources.c Date: Wed, 30 Mar 2022 12:07:14 +0200 Message-Id: <20220330100728.871561-39-sr@denx.de> In-Reply-To: <20220330100728.871561-1-sr@denx.de> References: <20220330100728.871561-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-pko3-resources.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/cvmx-pko3-resources.c | 229 ++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-pko3-resources.c diff --git a/arch/mips/mach-octeon/cvmx-pko3-resources.c b/arch/mips/mach-octeon/cvmx-pko3-resources.c new file mode 100644 index 000000000000..3d17d84832cf --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-pko3-resources.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * PKO resources. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#define CVMX_GR_TAG_PKO_PORT_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'p', 'o', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_L2_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '2', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_L3_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '3', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_L4_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '4', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_L5_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '5', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_DESCR_QUEUES(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'd', 'e', 'q', '_', \ + ((x) + '0'), '.', '.', '.', '.') +#define CVMX_GR_TAG_PKO_PORT_INDEX(x) \ + cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'p', 'i', 'd', '_', \ + ((x) + '0'), '.', '.', '.', '.') + +/* + * @INRWENAL + * Per-DQ parameters, current and maximum queue depth counters + */ +cvmx_pko3_dq_params_t *__cvmx_pko3_dq_params[CVMX_MAX_NODES]; + +static const short cvmx_pko_num_queues_78XX[256] = { + [CVMX_PKO_PORT_QUEUES] = 32, [CVMX_PKO_L2_QUEUES] = 512, + [CVMX_PKO_L3_QUEUES] = 512, [CVMX_PKO_L4_QUEUES] = 1024, + [CVMX_PKO_L5_QUEUES] = 1024, [CVMX_PKO_DESCR_QUEUES] = 1024 +}; + +static const short cvmx_pko_num_queues_73XX[256] = { + [CVMX_PKO_PORT_QUEUES] = 16, [CVMX_PKO_L2_QUEUES] = 256, + [CVMX_PKO_L3_QUEUES] = 256, [CVMX_PKO_L4_QUEUES] = 0, + [CVMX_PKO_L5_QUEUES] = 0, [CVMX_PKO_DESCR_QUEUES] = 256 +}; + +int cvmx_pko3_num_level_queues(enum cvmx_pko3_level_e level) +{ + unsigned int nq = 0, ne = 0; + + if (OCTEON_IS_MODEL(OCTEON_CN78XX)) { + ne = NUM_ELEMENTS(cvmx_pko_num_queues_78XX); + nq = cvmx_pko_num_queues_78XX[level]; + } + if (OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX)) { + ne = NUM_ELEMENTS(cvmx_pko_num_queues_73XX); + nq = cvmx_pko_num_queues_73XX[level]; + } + + if (nq == 0 || level >= ne) { + printf("ERROR: %s: queue level %#x invalid\n", __func__, level); + return -1; + } + + return nq; +} + +static inline struct global_resource_tag +__cvmx_pko_get_queues_resource_tag(int node, enum cvmx_pko3_level_e queue_level) +{ + if (cvmx_pko3_num_level_queues(queue_level) == 0) { + printf("ERROR: %s: queue level %#x invalid\n", __func__, + queue_level); + return CVMX_GR_TAG_INVALID; + } + + switch (queue_level) { + case CVMX_PKO_PORT_QUEUES: + return CVMX_GR_TAG_PKO_PORT_QUEUES(node); + case CVMX_PKO_L2_QUEUES: + return CVMX_GR_TAG_PKO_L2_QUEUES(node); + case CVMX_PKO_L3_QUEUES: + return CVMX_GR_TAG_PKO_L3_QUEUES(node); + case CVMX_PKO_L4_QUEUES: + return CVMX_GR_TAG_PKO_L4_QUEUES(node); + case CVMX_PKO_L5_QUEUES: + return CVMX_GR_TAG_PKO_L5_QUEUES(node); + case CVMX_PKO_DESCR_QUEUES: + return CVMX_GR_TAG_PKO_DESCR_QUEUES(node); + default: + printf("ERROR: %s: queue level %#x invalid\n", __func__, + queue_level); + return CVMX_GR_TAG_INVALID; + } +} + +/** + * Allocate or reserve a pko resource - called by wrapper functions + * @param tag processed global resource tag + * @param base_queue if specified the queue to reserve + * @param owner to be specified for resource + * @param num_queues to allocate + * @param max_num_queues for global resource + */ +int cvmx_pko_alloc_global_resource(struct global_resource_tag tag, + int base_queue, int owner, int num_queues, + int max_num_queues) +{ + int res; + + if (cvmx_create_global_resource_range(tag, max_num_queues)) { + debug("ERROR: Failed to create PKO3 resource: %lx-%lx\n", + (unsigned long)tag.hi, (unsigned long)tag.lo); + return -1; + } + if (base_queue >= 0) { + res = cvmx_reserve_global_resource_range(tag, owner, base_queue, + num_queues); + } else { + res = cvmx_allocate_global_resource_range(tag, owner, + num_queues, 1); + } + if (res < 0) { + debug("ERROR: Failed to %s PKO3 tag %lx:%lx, %i %i %i %i.\n", + ((base_queue < 0) ? "allocate" : "reserve"), + (unsigned long)tag.hi, (unsigned long)tag.lo, base_queue, + owner, num_queues, max_num_queues); + return -1; + } + + return res; +} + +/** + * Allocate or reserve PKO queues - wrapper for cvmx_pko_alloc_global_resource + * + * @param node on which to allocate/reserve PKO queues + * @param level of PKO queue + * @param owner of reserved/allocated resources + * @param base_queue to start reservation/allocatation + * @param num_queues number of queues to be allocated + * @return 0 on success, -1 on failure + */ +int cvmx_pko_alloc_queues(int node, int level, int owner, int base_queue, + int num_queues) +{ + struct global_resource_tag tag = + __cvmx_pko_get_queues_resource_tag(node, level); + int max_num_queues = cvmx_pko3_num_level_queues(level); + + return cvmx_pko_alloc_global_resource(tag, base_queue, owner, + num_queues, max_num_queues); +} + +/** + * Free an allocated/reserved PKO queues for a certain level and owner + * + * @param node on which to allocate/reserve PKO queues + * @param level of PKO queue + * @param owner of reserved/allocated resources + * @return 0 on success, -1 on failure + */ +int cvmx_pko_free_queues(int node, int level, int owner) +{ + struct global_resource_tag tag = + __cvmx_pko_get_queues_resource_tag(node, level); + + return cvmx_free_global_resource_range_with_owner(tag, owner); +} + +/** + * @INTERNAL + * + * Initialize the pointer to the descriptor queue parameter table. + * The table is one named block per node, and may be shared between + * applications. + */ +int __cvmx_pko3_dq_param_setup(unsigned int node) +{ + return 0; +} -- 2.35.1