From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF8D9C433EF for ; Wed, 30 Mar 2022 10:14:53 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0950E84167; Wed, 30 Mar 2022 12:11:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648635101; bh=fRbSNE+uIMzJPH0LxLeODw190Dwpp++K33JMPhxHge0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=o9cn3ypDrnsym/TFs+cyLWnAXfz1T4k5IsmiHbk6lqxVpogNHqZIict34iu6UETNL cmEKotRmn+UaVI/C9cVIMHm3TQYdZjf0MKvaSLW28WKbWiclPt/zYRh1qDRXAJ/dfh w9q1x2gWhjnDUDtNx7aOhxfPTJG0TiCgZEu+bzyjKYL/64QnianONfUrKFdNy1V2/F LBXpeilcf04xcgFhBk+xvFU+BZOVrNEBk2bQaD4nMbnK5qQB+0FJdLElY5keBOVojS b5w9ovdvqcb1Csfk6rST7e5plmd5K/HoS0asIKdAH7wqd1L+8Ko7xtuBti0NyemYDu TCMOsJBPICYYw== Received: by phobos.denx.de (Postfix, from userid 109) id 350C8840F9; Wed, 30 Mar 2022 12:09:18 +0200 (CEST) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9FA0A84104 for ; Wed, 30 Mar 2022 12:08:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (unknown [91.198.250.119]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4KT2F54tCSz9sRL; Wed, 30 Mar 2022 12:08:09 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH 39/52] mips: octeon: Add cvmx-pko-internal-ports-range.c Date: Wed, 30 Mar 2022 12:07:15 +0200 Message-Id: <20220330100728.871561-40-sr@denx.de> In-Reply-To: <20220330100728.871561-1-sr@denx.de> References: <20220330100728.871561-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-pko-internal-ports-range.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../cvmx-pko-internal-ports-range.c | 164 ++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c diff --git a/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c b/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c new file mode 100644 index 000000000000..259453eacd5c --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +union interface_port { + struct { + int port; + int interface; + } s; + u64 u64; +}; + +static int dbg; + +static int port_range_init; + +int __cvmx_pko_internal_ports_range_init(void) +{ + int rv = 0; + + if (port_range_init) + return 0; + port_range_init = 1; + rv = cvmx_create_global_resource_range(CVMX_GR_TAG_PKO_IPORTS, + CVMX_HELPER_CFG_MAX_PKO_QUEUES); + if (rv != 0) + debug("ERROR : Failed to initialize pko internal port range\n"); + return rv; +} + +int cvmx_pko_internal_ports_alloc(int xiface, int port, u64 count) +{ + int ret_val = -1; + union interface_port inf_port; + struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface); + + __cvmx_pko_internal_ports_range_init(); + inf_port.s.interface = xi.interface; + inf_port.s.port = port; + ret_val = cvmx_allocate_global_resource_range(CVMX_GR_TAG_PKO_IPORTS, + inf_port.u64, count, 1); + if (dbg) + debug("internal port alloc : port=%02d base=%02d count=%02d\n", + (int)port, ret_val, (int)count); + if (ret_val == -1) + return ret_val; + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_port_base = ret_val; + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_num_ports = count; + return 0; +} + +/* + * Return the internal ports base + * + * @param port the port for which the queues are returned + * + * @return 0 on success + * -1 on failure + */ +int cvmx_pko_internal_ports_free(int xiface, int port) +{ + struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface); + int ret_val = -1; + + __cvmx_pko_internal_ports_range_init(); + ret_val = cvmx_free_global_resource_range_with_base( + CVMX_GR_TAG_PKO_IPORTS, + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_port_base, + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_num_ports); + if (ret_val != 0) + return ret_val; + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_port_base = + CVMX_HELPER_CFG_INVALID_VALUE; + cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_num_ports = + CVMX_HELPER_CFG_INVALID_VALUE; + + return 0; +} + +void cvmx_pko_internal_ports_range_free_all(void) +{ + int interface, port; + + __cvmx_pko_internal_ports_range_init(); + for (interface = 0; interface < CVMX_HELPER_MAX_IFACE; interface++) + for (port = 0; port < CVMX_HELPER_CFG_MAX_PORT_PER_IFACE; + port++) { + if (cvmx_cfg_port[0][interface][port] + .ccpp_pko_port_base != + CVMX_HELPER_CFG_INVALID_VALUE) + cvmx_pko_internal_ports_free(interface, port); + } + //cvmx_range_show(pko_internal_ports_range); +} + +void cvmx_pko_internal_ports_range_show(void) +{ + int interface, port; + + __cvmx_pko_internal_ports_range_init(); + cvmx_show_global_resource_range(CVMX_GR_TAG_PKO_IPORTS); + for (interface = 0; interface < CVMX_HELPER_MAX_IFACE; interface++) + for (port = 0; port < CVMX_HELPER_CFG_MAX_PORT_PER_IFACE; + port++) { + if (cvmx_cfg_port[0][interface][port] + .ccpp_pko_port_base != + CVMX_HELPER_CFG_INVALID_VALUE) + debug("interface=%d port=%d port_base=%d port_cnt=%d\n", + interface, port, + (int)cvmx_cfg_port[0][interface][port] + .ccpp_pko_port_base, + (int)cvmx_cfg_port[0][interface][port] + .ccpp_pko_num_ports); + } +} -- 2.35.1