From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Cc: awilliams@marvell.com, cchavva@marvell.com
Subject: [PATCH 41/52] mips: octeon: Add cvmx-range.c
Date: Wed, 30 Mar 2022 12:07:17 +0200 [thread overview]
Message-ID: <20220330100728.871561-42-sr@denx.de> (raw)
In-Reply-To: <20220330100728.871561-1-sr@denx.de>
From: Aaron Williams <awilliams@marvell.com>
Import cvmx-range.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/mips/mach-octeon/cvmx-range.c | 344 +++++++++++++++++++++++++++++
1 file changed, 344 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-range.c
diff --git a/arch/mips/mach-octeon/cvmx-range.c b/arch/mips/mach-octeon/cvmx-range.c
new file mode 100644
index 000000000000..33dd95e7ab1a
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-range.c
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include <log.h>
+#include <time.h>
+#include <linux/delay.h>
+
+#include <mach/cvmx-regs.h>
+#include <mach/cvmx-csr.h>
+#include <mach/cvmx-bootmem.h>
+#include <mach/octeon-model.h>
+#include <mach/cvmx-fuse.h>
+#include <mach/octeon-feature.h>
+#include <mach/cvmx-qlm.h>
+#include <mach/octeon_qlm.h>
+#include <mach/cvmx-pcie.h>
+#include <mach/cvmx-coremask.h>
+
+#include <mach/cvmx-global-resources.h>
+
+#include <mach/cvmx-pki.h>
+#include <mach/cvmx-helper.h>
+#include <mach/cvmx-helper-board.h>
+#include <mach/cvmx-helper-cfg.h>
+
+#include <mach/cvmx-range.h>
+
+#define CVMX_RANGE_AVAILABLE ((u64)-88)
+#define addr_of_element(base, index) \
+ (1ull << 63 | ((base) + sizeof(u64) + (index) * sizeof(u64)))
+#define addr_of_size(base) (1ull << 63 | (base))
+
+static const int debug;
+
+int cvmx_range_memory_size(int nelements)
+{
+ return sizeof(u64) * (nelements + 1);
+}
+
+int cvmx_range_init(u64 range_addr, int size)
+{
+ u64 lsize = size;
+ u64 i;
+
+ cvmx_write64_uint64(addr_of_size(range_addr), lsize);
+ for (i = 0; i < lsize; i++) {
+ cvmx_write64_uint64(addr_of_element(range_addr, i),
+ CVMX_RANGE_AVAILABLE);
+ }
+ return 0;
+}
+
+static int64_t cvmx_range_find_next_available(u64 range_addr, u64 index,
+ int align)
+{
+ u64 size = cvmx_read64_uint64(addr_of_size(range_addr));
+ u64 i;
+
+ while ((index % align) != 0)
+ index++;
+
+ for (i = index; i < size; i += align) {
+ u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+
+ if (debug)
+ debug("%s: index=%d owner=%llx\n", __func__, (int)i,
+ (unsigned long long)r_owner);
+ if (r_owner == CVMX_RANGE_AVAILABLE)
+ return i;
+ }
+ return -1;
+}
+
+static int64_t cvmx_range_find_last_available(u64 range_addr, u64 index,
+ u64 align)
+{
+ u64 size = cvmx_read64_uint64(addr_of_size(range_addr));
+ u64 i;
+
+ if (index == 0)
+ index = size - 1;
+
+ while ((index % align) != 0)
+ index++;
+
+ for (i = index; i > align; i -= align) {
+ u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+
+ if (debug)
+ debug("%s: index=%d owner=%llx\n", __func__, (int)i,
+ (unsigned long long)r_owner);
+ if (r_owner == CVMX_RANGE_AVAILABLE)
+ return i;
+ }
+ return -1;
+}
+
+int cvmx_range_alloc_ordered(u64 range_addr, u64 owner, u64 cnt,
+ int align, int reverse)
+{
+ u64 i = 0, size;
+ s64 first_available;
+
+ if (debug)
+ debug("%s: range_addr=%llx owner=%llx cnt=%d\n", __func__,
+ (unsigned long long)range_addr,
+ (unsigned long long)owner, (int)cnt);
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ while (i < size) {
+ u64 available_cnt = 0;
+
+ if (reverse)
+ first_available = cvmx_range_find_last_available(range_addr, i, align);
+ else
+ first_available = cvmx_range_find_next_available(range_addr, i, align);
+ if (first_available == -1)
+ return -1;
+ i = first_available;
+
+ if (debug)
+ debug("%s: first_available=%d\n", __func__, (int)first_available);
+ while ((available_cnt != cnt) && (i < size)) {
+ u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+
+ if (r_owner == CVMX_RANGE_AVAILABLE)
+ available_cnt++;
+ i++;
+ }
+ if (available_cnt == cnt) {
+ u64 j;
+
+ if (debug)
+ debug("%s: first_available=%d available=%d\n",
+ __func__,
+ (int)first_available, (int)available_cnt);
+
+ for (j = first_available; j < first_available + cnt;
+ j++) {
+ u64 a = addr_of_element(range_addr, j);
+
+ cvmx_write64_uint64(a, owner);
+ }
+ return first_available;
+ }
+ }
+
+ if (debug) {
+ debug("ERROR: %s: failed to allocate range cnt=%d\n",
+ __func__, (int)cnt);
+ cvmx_range_show(range_addr);
+ }
+
+ return -1;
+}
+
+int cvmx_range_alloc(u64 range_addr, u64 owner, u64 cnt, int align)
+{
+ return cvmx_range_alloc_ordered(range_addr, owner, cnt, align, 0);
+}
+
+int cvmx_range_alloc_non_contiguos(u64 range_addr, u64 owner,
+ u64 cnt, int elements[])
+{
+ u64 i = 0, size;
+ u64 element_index = 0;
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ for (i = 0; i < size; i++) {
+ u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+
+ if (debug)
+ debug("%s: index=%d owner=%llx\n", __func__, (int)i,
+ (unsigned long long)r_owner);
+ if (r_owner == CVMX_RANGE_AVAILABLE)
+ elements[element_index++] = (int)i;
+
+ if (element_index == cnt)
+ break;
+ }
+ if (element_index != cnt) {
+ if (debug)
+ debug("%s: failed to allocate non contiguous cnt=%d available=%d\n",
+ __func__, (int)cnt, (int)element_index);
+ return -1;
+ }
+ for (i = 0; i < cnt; i++) {
+ u64 a = addr_of_element(range_addr, elements[i]);
+
+ cvmx_write64_uint64(a, owner);
+ }
+ return 0;
+}
+
+int cvmx_range_reserve(u64 range_addr, u64 owner, u64 base,
+ u64 cnt)
+{
+ u64 i, size, r_owner;
+ u64 up = base + cnt;
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ if (up > size) {
+ debug("ERROR: %s: invalid base or cnt. range_addr=0x%llx, owner=0x%llx, size=%d base+cnt=%d\n",
+ __func__, (unsigned long long)range_addr,
+ (unsigned long long)owner,
+ (int)size, (int)up);
+ return -1;
+ }
+ for (i = base; i < up; i++) {
+ r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+ if (debug)
+ debug("%s: %d: %llx\n",
+ __func__, (int)i, (unsigned long long)r_owner);
+ if (r_owner != CVMX_RANGE_AVAILABLE) {
+ if (debug) {
+ debug("%s: resource already reserved base+cnt=%d %llu %llu %llx %llx %llx\n",
+ __func__, (int)i, (unsigned long long)cnt,
+ (unsigned long long)base,
+ (unsigned long long)r_owner,
+ (unsigned long long)range_addr,
+ (unsigned long long)owner);
+ }
+ return -1;
+ }
+ }
+ for (i = base; i < up; i++)
+ cvmx_write64_uint64(addr_of_element(range_addr, i), owner);
+ return base;
+}
+
+int cvmx_range_free_with_owner(u64 range_addr, u64 owner)
+{
+ u64 i, size;
+ int found = -1;
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ for (i = 0; i < size; i++) {
+ u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i));
+
+ if (r_owner == owner) {
+ cvmx_write64_uint64(addr_of_element(range_addr, i),
+ CVMX_RANGE_AVAILABLE);
+ found = 0;
+ }
+ }
+ return found;
+}
+
+int __cvmx_range_is_allocated(u64 range_addr, int bases[], int count)
+{
+ u64 i, cnt, size;
+ u64 r_owner;
+
+ cnt = count;
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ for (i = 0; i < cnt; i++) {
+ u64 base = bases[i];
+
+ if (base >= size) {
+ debug("ERROR: %s: invalid base or cnt size=%d base=%d\n",
+ __func__, (int)size, (int)base);
+ return 0;
+ }
+ r_owner = cvmx_read64_uint64(addr_of_element(range_addr, base));
+ if (r_owner == CVMX_RANGE_AVAILABLE) {
+ if (debug) {
+ debug("%s: i=%d:base=%d is available\n",
+ __func__, (int)i, (int)base);
+ }
+ return 0;
+ }
+ }
+ return 1;
+}
+
+int cvmx_range_free_mutiple(u64 range_addr, int bases[], int count)
+{
+ u64 i, cnt;
+
+ cnt = count;
+ if (__cvmx_range_is_allocated(range_addr, bases, count) != 1)
+ return -1;
+ for (i = 0; i < cnt; i++) {
+ u64 base = bases[i];
+
+ cvmx_write64_uint64(addr_of_element(range_addr, base),
+ CVMX_RANGE_AVAILABLE);
+ }
+ return 0;
+}
+
+int cvmx_range_free_with_base(u64 range_addr, int base, int cnt)
+{
+ u64 i, size;
+ u64 up = base + cnt;
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ if (up > size) {
+ debug("ERROR: %s: invalid base or cnt size=%d base+cnt=%d\n",
+ __func__, (int)size, (int)up);
+ return -1;
+ }
+ for (i = base; i < up; i++) {
+ cvmx_write64_uint64(addr_of_element(range_addr, i),
+ CVMX_RANGE_AVAILABLE);
+ }
+ return 0;
+}
+
+u64 cvmx_range_get_owner(u64 range_addr, u64 base)
+{
+ u64 size = cvmx_read64_uint64(addr_of_size(range_addr));
+
+ if (base >= size) {
+ debug("ERROR: %s: invalid base or cnt size=%d base=%d\n",
+ __func__, (int)size, (int)base);
+ return 0;
+ }
+ return cvmx_read64_uint64(addr_of_element(range_addr, base));
+}
+
+void cvmx_range_show(u64 range_addr)
+{
+ u64 pval, val, size, pindex, i;
+
+ size = cvmx_read64_uint64(addr_of_size(range_addr));
+ pval = cvmx_read64_uint64(addr_of_element(range_addr, 0));
+ pindex = 0;
+
+ debug("index=%d: owner %llx\n", (int)pindex, CAST_ULL(pval));
+
+ for (i = 1; i < size; i++) {
+ val = cvmx_read64_uint64(addr_of_element(range_addr, i));
+ if (val != pval) {
+ debug("index=%d: owner %llx\n", (int)pindex,
+ CAST_ULL(pval));
+ pindex = i;
+ pval = val;
+ }
+ }
+ debug("index=%d: owner %llx\n", (int)pindex, CAST_ULL(pval));
+}
--
2.35.1
next prev parent reply other threads:[~2022-03-30 10:18 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-30 10:06 [PATCH 00/52] mips: octeon: Add ethernet support Stefan Roese
2022-03-30 10:06 ` [PATCH 01/52] mips: octeon: Add misc cvmx-* header files Stefan Roese
2022-03-30 10:06 ` [PATCH 02/52] mips: octeon: Add cvmx-ilk-defs.h header file Stefan Roese
2022-03-30 10:06 ` [PATCH 03/52] mips: octeon: Add cvmx-iob-defs.h " Stefan Roese
2022-03-30 10:06 ` [PATCH 04/52] mips: octeon: Add cvmx-lbk-defs.h " Stefan Roese
2022-03-30 10:06 ` [PATCH 05/52] mips: octeon: Add cvmx-npei-defs.h " Stefan Roese
2022-03-30 10:06 ` [PATCH 06/52] mips: octeon: Add cvmx-pcsxx-defs.h " Stefan Roese
2022-03-30 10:06 ` [PATCH 07/52] mips: octeon: Add cvmx-xcv-defs.h " Stefan Roese
2022-03-30 10:06 ` [PATCH 08/52] mips: octeon: Misc changes to existing headers for upcoming eth support Stefan Roese
2022-03-30 10:06 ` [PATCH 09/52] mips: octeon: Add cvmx-helper-agl.c Stefan Roese
2022-03-30 10:06 ` [PATCH 10/52] mips: octeon: Add cvmx-helper-bgx.c Stefan Roese
2022-03-30 10:06 ` [PATCH 11/52] mips: octeon: Add cvmx-helper-board.c Stefan Roese
2022-03-30 10:06 ` [PATCH 12/52] mips: octeon: Add cvmx-helper-fpa.c Stefan Roese
2022-03-30 10:06 ` [PATCH 13/52] mips: octeon: Add cvmx-helper-igl.c Stefan Roese
2022-03-30 10:06 ` [PATCH 14/52] mips: octeon: Add cvmx-helper-ipd.c Stefan Roese
2022-03-30 10:06 ` [PATCH 15/52] mips: octeon: Add cvmx-helper-loop.c Stefan Roese
2022-03-30 10:06 ` [PATCH 17/52] mips: octeon: Add cvmx-helper-pki.c Stefan Roese
2022-03-30 10:06 ` [PATCH 18/52] mips: octeon: Add cvmx-helper-pko.c Stefan Roese
2022-03-30 10:06 ` [PATCH 19/52] mips: octeon: Add cvmx-helper-pko3.c Stefan Roese
2022-03-30 10:06 ` [PATCH 20/52] mips: octeon: Add cvmx-helper-rgmii.c Stefan Roese
2022-03-30 10:06 ` [PATCH 21/52] mips: octeon: Add cvmx-helper-sgmii.c Stefan Roese
2022-03-30 10:06 ` [PATCH 22/52] mips: octeon: Add cvmx-helper-sfp.c Stefan Roese
2022-03-30 10:07 ` [PATCH 24/52] mips: octeon: Add cvmx-agl.c Stefan Roese
2022-03-30 10:07 ` [PATCH 25/52] mips: octeon: Add cvmx-cmd-queue.c Stefan Roese
2022-03-30 10:07 ` [PATCH 26/52] mips: octeon: Add cvmx-fau-compat.c Stefan Roese
2022-03-30 10:07 ` [PATCH 28/52] mips: octeon: Add cvmx-fpa-resource.c Stefan Roese
2022-03-30 10:07 ` [PATCH 29/52] mips: octeon: Add cvmx-global-resource.c Stefan Roese
2022-03-30 10:07 ` [PATCH 30/52] mips: octeon: Add cvmx-ilk.c Stefan Roese
2022-03-30 10:07 ` [PATCH 31/52] mips: octeon: Add cvmx-ipd.c Stefan Roese
2022-03-30 10:07 ` [PATCH 32/52] mips: octeon: Add cvmx-pki.c Stefan Roese
2022-03-30 10:07 ` [PATCH 34/52] mips: octeon: Add cvmx-pko.c Stefan Roese
2022-03-30 10:07 ` [PATCH 35/52] mips: octeon: Add cvmx-pko3.c Stefan Roese
2022-03-30 10:07 ` [PATCH 36/52] mips: octeon: Add cvmx-pko3-queue.c Stefan Roese
2022-03-30 10:07 ` [PATCH 37/52] mips: octeon: Add cvmx-pko3-compat.c Stefan Roese
2022-03-30 10:07 ` [PATCH 38/52] mips: octeon: Add cvmx-pko3-resources.c Stefan Roese
2022-03-30 10:07 ` [PATCH 39/52] mips: octeon: Add cvmx-pko-internal-ports-range.c Stefan Roese
2022-03-30 10:07 ` [PATCH 40/52] mips: octeon: Add cvmx-qlm-tables.c Stefan Roese
2022-03-30 10:07 ` Stefan Roese [this message]
2022-03-30 10:07 ` [PATCH 42/52] mips: octeon: Misc changes to existing C files for upcoming eth support Stefan Roese
2022-03-30 10:07 ` [PATCH 43/52] mips: octeon: Makefile: Enable building of the newly added C files Stefan Roese
2022-03-30 10:07 ` [PATCH 44/52] mips: octeon: cpu.c: Move bootmem init to arch_early_init_r() Stefan Roese
2022-03-30 10:07 ` [PATCH 45/52] mips: octeon: cpu.c: Implement configure_lmtdma_window() Stefan Roese
2022-03-30 10:07 ` [PATCH 46/52] mips: octeon: octeon_common.h: Move init SP because of increased image size Stefan Roese
2022-03-30 10:07 ` [PATCH 47/52] mips: octeon: mrvl, cn73xx.dtsi: Add ethernet (BGX) and SMI DT nodes Stefan Roese
2022-03-30 10:07 ` [PATCH 48/52] mips: octeon: mrvl, octeon-ebb7304.dts: Add ethernet DT support Stefan Roese
2022-03-30 10:07 ` [PATCH 49/52] mips: octeon: mrvl, octeon-nic23.dts: " Stefan Roese
2022-03-30 10:07 ` [PATCH 50/52] net: Add ethernet support for MIPS Octeon Stefan Roese
2022-03-30 10:07 ` [PATCH 51/52] mips: octeon: ebb7304: Enable ethernet support Stefan Roese
2022-03-30 10:07 ` [PATCH 52/52] mips: octeon: nic23: " Stefan Roese
2022-03-30 10:30 ` [PATCH 00/52] mips: octeon: Add " Stefan Roese
2022-03-30 23:56 ` Daniel Schwierzeck
2022-03-31 5:27 ` Stefan Roese
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