From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E7B3C433F5 for ; Wed, 30 Mar 2022 10:18:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CF274841A5; Wed, 30 Mar 2022 12:13:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1648635183; bh=wYtwrxHg/6Gt2EJKlBcSDUj68QB5sLpHOYlCu4/EqJE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=NjMZ7q8GeWoohNE+dKtFHC1GrpCSOte98dh9xNt9lWfFuMusmJQfecsiKi9ksWM8k j4eFWBkvQL1j9keGU2RtWdi1xg6lOPyHGYxgutweuORClpbufEZ65pWRmrOH57yNik rE3T4sCmC13fRpBVpLUd8SIHW5rLryxLqsJQnVG+PRbFgwBKKQmbLjORGOAP6n8HJx 4PE+mHbigIwIc/McvAloZsWtwSSno6PBmSbd+C6pMe+K/2Pid/xtMeU8iSJcGvAJy3 yXuF0BLIewWJjrRwr+tmcP9RpuAhn8Nn/255bIcQq7iD2kWicZOVD5Zu3ojlqKYTj+ 6PImWWM3lH42A== Received: by phobos.denx.de (Postfix, from userid 109) id BA23684128; Wed, 30 Mar 2022 12:08:45 +0200 (CEST) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ED89E840F7 for ; Wed, 30 Mar 2022 12:08:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:105:465:1:3:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4KT2F70s34z9sRm; Wed, 30 Mar 2022 12:08:11 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH 41/52] mips: octeon: Add cvmx-range.c Date: Wed, 30 Mar 2022 12:07:17 +0200 Message-Id: <20220330100728.871561-42-sr@denx.de> In-Reply-To: <20220330100728.871561-1-sr@denx.de> References: <20220330100728.871561-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-range.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/cvmx-range.c | 344 +++++++++++++++++++++++++++++ 1 file changed, 344 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-range.c diff --git a/arch/mips/mach-octeon/cvmx-range.c b/arch/mips/mach-octeon/cvmx-range.c new file mode 100644 index 000000000000..33dd95e7ab1a --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-range.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#define CVMX_RANGE_AVAILABLE ((u64)-88) +#define addr_of_element(base, index) \ + (1ull << 63 | ((base) + sizeof(u64) + (index) * sizeof(u64))) +#define addr_of_size(base) (1ull << 63 | (base)) + +static const int debug; + +int cvmx_range_memory_size(int nelements) +{ + return sizeof(u64) * (nelements + 1); +} + +int cvmx_range_init(u64 range_addr, int size) +{ + u64 lsize = size; + u64 i; + + cvmx_write64_uint64(addr_of_size(range_addr), lsize); + for (i = 0; i < lsize; i++) { + cvmx_write64_uint64(addr_of_element(range_addr, i), + CVMX_RANGE_AVAILABLE); + } + return 0; +} + +static int64_t cvmx_range_find_next_available(u64 range_addr, u64 index, + int align) +{ + u64 size = cvmx_read64_uint64(addr_of_size(range_addr)); + u64 i; + + while ((index % align) != 0) + index++; + + for (i = index; i < size; i += align) { + u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + + if (debug) + debug("%s: index=%d owner=%llx\n", __func__, (int)i, + (unsigned long long)r_owner); + if (r_owner == CVMX_RANGE_AVAILABLE) + return i; + } + return -1; +} + +static int64_t cvmx_range_find_last_available(u64 range_addr, u64 index, + u64 align) +{ + u64 size = cvmx_read64_uint64(addr_of_size(range_addr)); + u64 i; + + if (index == 0) + index = size - 1; + + while ((index % align) != 0) + index++; + + for (i = index; i > align; i -= align) { + u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + + if (debug) + debug("%s: index=%d owner=%llx\n", __func__, (int)i, + (unsigned long long)r_owner); + if (r_owner == CVMX_RANGE_AVAILABLE) + return i; + } + return -1; +} + +int cvmx_range_alloc_ordered(u64 range_addr, u64 owner, u64 cnt, + int align, int reverse) +{ + u64 i = 0, size; + s64 first_available; + + if (debug) + debug("%s: range_addr=%llx owner=%llx cnt=%d\n", __func__, + (unsigned long long)range_addr, + (unsigned long long)owner, (int)cnt); + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + while (i < size) { + u64 available_cnt = 0; + + if (reverse) + first_available = cvmx_range_find_last_available(range_addr, i, align); + else + first_available = cvmx_range_find_next_available(range_addr, i, align); + if (first_available == -1) + return -1; + i = first_available; + + if (debug) + debug("%s: first_available=%d\n", __func__, (int)first_available); + while ((available_cnt != cnt) && (i < size)) { + u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + + if (r_owner == CVMX_RANGE_AVAILABLE) + available_cnt++; + i++; + } + if (available_cnt == cnt) { + u64 j; + + if (debug) + debug("%s: first_available=%d available=%d\n", + __func__, + (int)first_available, (int)available_cnt); + + for (j = first_available; j < first_available + cnt; + j++) { + u64 a = addr_of_element(range_addr, j); + + cvmx_write64_uint64(a, owner); + } + return first_available; + } + } + + if (debug) { + debug("ERROR: %s: failed to allocate range cnt=%d\n", + __func__, (int)cnt); + cvmx_range_show(range_addr); + } + + return -1; +} + +int cvmx_range_alloc(u64 range_addr, u64 owner, u64 cnt, int align) +{ + return cvmx_range_alloc_ordered(range_addr, owner, cnt, align, 0); +} + +int cvmx_range_alloc_non_contiguos(u64 range_addr, u64 owner, + u64 cnt, int elements[]) +{ + u64 i = 0, size; + u64 element_index = 0; + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + for (i = 0; i < size; i++) { + u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + + if (debug) + debug("%s: index=%d owner=%llx\n", __func__, (int)i, + (unsigned long long)r_owner); + if (r_owner == CVMX_RANGE_AVAILABLE) + elements[element_index++] = (int)i; + + if (element_index == cnt) + break; + } + if (element_index != cnt) { + if (debug) + debug("%s: failed to allocate non contiguous cnt=%d available=%d\n", + __func__, (int)cnt, (int)element_index); + return -1; + } + for (i = 0; i < cnt; i++) { + u64 a = addr_of_element(range_addr, elements[i]); + + cvmx_write64_uint64(a, owner); + } + return 0; +} + +int cvmx_range_reserve(u64 range_addr, u64 owner, u64 base, + u64 cnt) +{ + u64 i, size, r_owner; + u64 up = base + cnt; + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + if (up > size) { + debug("ERROR: %s: invalid base or cnt. range_addr=0x%llx, owner=0x%llx, size=%d base+cnt=%d\n", + __func__, (unsigned long long)range_addr, + (unsigned long long)owner, + (int)size, (int)up); + return -1; + } + for (i = base; i < up; i++) { + r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + if (debug) + debug("%s: %d: %llx\n", + __func__, (int)i, (unsigned long long)r_owner); + if (r_owner != CVMX_RANGE_AVAILABLE) { + if (debug) { + debug("%s: resource already reserved base+cnt=%d %llu %llu %llx %llx %llx\n", + __func__, (int)i, (unsigned long long)cnt, + (unsigned long long)base, + (unsigned long long)r_owner, + (unsigned long long)range_addr, + (unsigned long long)owner); + } + return -1; + } + } + for (i = base; i < up; i++) + cvmx_write64_uint64(addr_of_element(range_addr, i), owner); + return base; +} + +int cvmx_range_free_with_owner(u64 range_addr, u64 owner) +{ + u64 i, size; + int found = -1; + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + for (i = 0; i < size; i++) { + u64 r_owner = cvmx_read64_uint64(addr_of_element(range_addr, i)); + + if (r_owner == owner) { + cvmx_write64_uint64(addr_of_element(range_addr, i), + CVMX_RANGE_AVAILABLE); + found = 0; + } + } + return found; +} + +int __cvmx_range_is_allocated(u64 range_addr, int bases[], int count) +{ + u64 i, cnt, size; + u64 r_owner; + + cnt = count; + size = cvmx_read64_uint64(addr_of_size(range_addr)); + for (i = 0; i < cnt; i++) { + u64 base = bases[i]; + + if (base >= size) { + debug("ERROR: %s: invalid base or cnt size=%d base=%d\n", + __func__, (int)size, (int)base); + return 0; + } + r_owner = cvmx_read64_uint64(addr_of_element(range_addr, base)); + if (r_owner == CVMX_RANGE_AVAILABLE) { + if (debug) { + debug("%s: i=%d:base=%d is available\n", + __func__, (int)i, (int)base); + } + return 0; + } + } + return 1; +} + +int cvmx_range_free_mutiple(u64 range_addr, int bases[], int count) +{ + u64 i, cnt; + + cnt = count; + if (__cvmx_range_is_allocated(range_addr, bases, count) != 1) + return -1; + for (i = 0; i < cnt; i++) { + u64 base = bases[i]; + + cvmx_write64_uint64(addr_of_element(range_addr, base), + CVMX_RANGE_AVAILABLE); + } + return 0; +} + +int cvmx_range_free_with_base(u64 range_addr, int base, int cnt) +{ + u64 i, size; + u64 up = base + cnt; + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + if (up > size) { + debug("ERROR: %s: invalid base or cnt size=%d base+cnt=%d\n", + __func__, (int)size, (int)up); + return -1; + } + for (i = base; i < up; i++) { + cvmx_write64_uint64(addr_of_element(range_addr, i), + CVMX_RANGE_AVAILABLE); + } + return 0; +} + +u64 cvmx_range_get_owner(u64 range_addr, u64 base) +{ + u64 size = cvmx_read64_uint64(addr_of_size(range_addr)); + + if (base >= size) { + debug("ERROR: %s: invalid base or cnt size=%d base=%d\n", + __func__, (int)size, (int)base); + return 0; + } + return cvmx_read64_uint64(addr_of_element(range_addr, base)); +} + +void cvmx_range_show(u64 range_addr) +{ + u64 pval, val, size, pindex, i; + + size = cvmx_read64_uint64(addr_of_size(range_addr)); + pval = cvmx_read64_uint64(addr_of_element(range_addr, 0)); + pindex = 0; + + debug("index=%d: owner %llx\n", (int)pindex, CAST_ULL(pval)); + + for (i = 1; i < size; i++) { + val = cvmx_read64_uint64(addr_of_element(range_addr, i)); + if (val != pval) { + debug("index=%d: owner %llx\n", (int)pindex, + CAST_ULL(pval)); + pindex = i; + pval = val; + } + } + debug("index=%d: owner %llx\n", (int)pindex, CAST_ULL(pval)); +} -- 2.35.1