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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id h2-20020ac85842000000b002e1ec550506sm17749694qth.87.2022.03.30.15.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Mar 2022 15:07:54 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Cc: Priyanka Jain , Rajesh Bhagat Subject: [PATCH 25/25] arm: fsl-layerscape: Migrate more DP-DDR options to Kconfig Date: Wed, 30 Mar 2022 18:07:35 -0400 Message-Id: <20220330220735.908616-25-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220330220735.908616-1-trini@konsulko.com> References: <20220330220735.908616-1-trini@konsulko.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Based on current usage, migrate a number of DP-DDR related options to Kconfig. Cc: Priyanka Jain Cc: Rajesh Bhagat Signed-off-by: Tom Rini --- README | 3 --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 25 +++++++++++++++++++++++ include/configs/ls2080a_common.h | 10 --------- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/README b/README index 6273a7f3673e..d503357f3be2 100644 --- a/README +++ b/README @@ -487,9 +487,6 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. - CONFIG_SYS_FSL_HAS_DP_DDR - Defines the SoC has DP-DDR used for DPAA. - CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9bb870dcd8c2..5ea99c459ce7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -502,6 +502,31 @@ config SYS_FSL_HAS_CCN508 config SYS_FSL_HAS_DP_DDR bool + help + Defines the SoC has DP-DDR used for DPAA. + +config DP_DDR_CTRL + int + depends on SYS_FSL_HAS_DP_DDR + default 2 if ARCH_LS2080A + +config DP_DDR_NUM_CTRLS + int + depends on SYS_FSL_HAS_DP_DDR + default 1 if ARCH_LS2080A + +config SYS_DP_DDR_BASE + hex + depends on SYS_FSL_HAS_DP_DDR + default 0x6000000000 if ARCH_LS2080A + +config SYS_DP_DDR_BASE_PHY + int + depends on SYS_FSL_HAS_DP_DDR + default 0 if ARCH_LS2080A + help + DDR controller uses this value as the base address for binding. + It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. config SYS_FSL_SRDS_1 bool diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 9027bd06b02d..82585f5dbfaf 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -40,16 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL -/* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ -#define CONFIG_SYS_DP_DDR_BASE_PHY 0 -#define CONFIG_DP_DDR_CTRL 2 -#define CONFIG_DP_DDR_NUM_CTRLS 1 -#endif /* Generic Timer Definitions */ /* -- 2.25.1